Electrical Contact Resistance of Large-Area Graphene on Pre-Patterned Cu and Au Electrodes

Contact resistance between electrically connected parts of electronic elements can negatively affect their resulting properties and parameters. The contact resistance is influenced by the physicochemical properties of the connected elements and, in most cases, the lowest possible value is required. The issue of contact resistance is also addressed in connection with the increasingly frequently used carbon allotropes. This work aimed to determine the factors that influence contact resistance between graphene prepared by chemical vapour deposition and pre-patterned Cu and Au electrodes onto which graphene is subsequently transferred. It was found that electrode surface treatment methods affect the resistance between Cu and graphene, where contact resistance varied greatly, with an average of 1.25 ± 1.54 kΩ, whereas for the Au electrodes, the deposition techniques did not influence the resulting contact resistance, which decreased by almost two orders of magnitude compared with the Cu electrodes, to 0.03 ± 0.01 kΩ

Electrical Contact Resistance of Large-Area Graphene on Pre-Patterned Cu and Au Electrodes

Contact resistance between electrically connected parts of electronic elements can negatively affect their resulting properties and parameters. The contact resistance is influenced by the physicochemical properties of the connected elements and, in most cases, the lowest possible value is required. The issue of contact resistance is also addressed in connection with the increasingly frequently used carbon allotropes. This work aimed to determine the factors that influence contact resistance between graphene prepared by chemical vapour deposition and pre-patterned Cu and Au electrodes onto which graphene is subsequently transferred. It was found that electrode surface treatment methods affect the resistance between Cu and graphene, where contact resistance varied greatly, with an average of 1.25 ± 1.54 kΩ, whereas for the Au electrodes, the deposition techniques did not influence the resulting contact resistance, which decreased by almost two orders of magnitude compared with the Cu electrodes, to 0.03 ± 0.01 kΩ.Contact resistance between electrically connected parts of electronic elements can negatively affect their resulting properties and parameters. The contact resistance is influenced by the physicochemical properties of the connected elements and, in most cases, the lowest possible value is required. The issue of contact resistance is also addressed in connection with the increasingly frequently used carbon allotropes. This work aimed to determine the factors that influence contact resistance between graphene prepared by chemical vapour deposition and pre-patterned Cu and Au electrodes onto which graphene is subsequently transferred. It was found that electrode surface treatment methods affect the resistance between Cu and graphene, where contact resistance varied greatly, with an average of 1.25 ± 1.54 kΩ, whereas for the Au electrodes, the deposition techniques did not influence the resulting contact resistance, which decreased by almost two orders of magnitude compared with the Cu electrodes, to 0.03 ± 0.01 kΩ

Electrical Characterisation of III-V Nanowire MOSFETs

The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

Recent Advances in Thin Film Electronic Devices

This reprint is a collection of the papers from the Special Issue “Recent Advances in Thin Film Electronic Devices” in Micromachines. In this reprrint, 1 editorial and 11 original papers about recent advances in the research and development of thin film electronic devices are included. Specifically, three research fields are covered: device fundamentals (5 papers), fabrication processes (5 papers), and testing methods (1 paper). The experimental data, simulation results, and theoretical analysis presented in this reprint should benefit those researchers in flat panel displays, flat panel sensors, energy devices, memories, and so on