Low-voltage current-mode CMOS filter structure for high frequency applications

Ankara : Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 1995.Thesis (Master's) -- Bilkent University, 1995.Includes bibliographical references leaves 49-50.In this thesis, a new method for the design of tunable current-mode CMOS filters is presented. The proposed structure is suitable for low-voltage (3V) and high frequency applications. Basic building blocks are differential damped integrator and differential damped differentiator, which have tunable comer frequencies. Using first order building blocks and applying feedback techniques, biquadratic sections of low-pass, high-pass and band-pass filters are generated. Higher order filters are implemented by using cascaded biquad synthesis. Filters are tuned by means of two control voltages, from 50% to 130% of their corner frequencies. HSPICE simulations show that filter implementation up to 0.5GHz is possible for 2.4^ CMOS technology. The available frequency range can be increased using a better technology such as 0.7/i CMOS. Layouts for two test chips are generated using CADENCE full-custom design environment for 0.7/i and 2.4/i CMOS processes.Karşılayan, Aydın İlkerM.S

Linear Optical Quantum Computing in a Single Spatial Mode

We present a scheme for linear optical quantum computing using time-bin encoded qubits in a single spatial mode. We show methods for single-qubit operations and heralded controlled phase (CPhase) gates, providing a sufficient set of operations for universal quantum computing with the Knill-Laflamme-Milburn scheme. Our scheme is suited to available photonic devices and ideally allows arbitrary numbers of qubits to be encoded in the same spatial mode, demonstrating the potential for time-frequency modes to dramatically increase the quantum information capacity of fixed spatial resources. As a test of our scheme, we demonstrate the first entirely single spatial mode implementation of a two-qubit quantum gate and show its operation with an average fidelity of 0.84+-0.07.Comment: 5 pages, 4 figures. Updated to be consistent with the published versio

On the Use of the p-q Theory for Harmonic Current Cancellation with Shunt Active Filters

Discussion and mathematical proof on necessary and sufficient conditions for the application of the {p-q} theory for compensating the harmonic currents consumed by non-linear load using a shunt active filter are presented. These conditions over instantaneous active and reactive powers were not addressed before and must be considered on the design of new control strategies based on {p-q} theory. Theoretical demonstration is proposed and an application example with simulations results is used to validate the theoretical results

A 0.18μm CMOS 9mW current-mode FLF linear phase filter with gain boost

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”The design and implementation of a CMOS continuous-time follow-the-leader-feedback (FLF) filter is described. The filter is implemented using a fully-differential linear, low voltage and low power consumption operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18 mum CMOS process with 2 V power supply have shown that the cut-off frequency of the filter ranges from 55 MHz to 160 MHz and dynamic range is about 45 dB. The group delay is less than 5% over the whole tuning range; the power consumption is only 9 mW

A CMOS 100 MHz continuous-time seventh order 0.05° equiripple linear phase leapfrog multiple loop feedback Gm-C filter

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A novel 100 MHz CMOS Gm-C seventh-order 0.05° equiripple linear phase low-pass multiple loop feedback (MLF) filter based on leapfrog (LF) topology is presented. The filter is implemented using a fully-differential linear, high performance operational transconductance amplifier (OTA) based on cross-coupled pairs. PSpice simulations in a standard TSMC 0.25 μm CMOS process and with a single 5 V power supply have shown that the cut-off frequency of the filter without and with gain boost ranges from 8-32 MHz and 15-100 MHz, respectively. With gain boost, total harmonic distortion (THD) for a differential input voltage Vid of 315 mVpp at 1 MHz is less than -40 dB, dynamic range at 1% THD is over 55 dB, output noise with bandwidth 500 MHz is only 300 μVRMS, and power consumption is 322 mW

CMOS current-mode chaotic neurons

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. They have been fabricated in a double-metal, single-poly 1.6 /spl mu/m CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploration of the exponential-law operation of CMOS-BJT's. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation

UMTV: a Single Chip TV Receiver for PDAs, PCs and Cell Phones

A zero-external-component TV receiver for portable platforms is realized in a mainstream 8GHz-f/sub t/ BiCMOS process. Die size is 5/spl times/5mm/sup 2/ and power dissipation is 50mA at 3V. The receiver includes a single tunable LNA (3mA) with less than 5dB NF from 40 to 900MHz. The programmable IF filters cover all analog and digital standards