Ball lens embedded through-package via to enable backside coupling between silicon photonics interposer and board-level interconnects

Development of an efficient and densely integrated optical coupling interface for silicon photonics based board-level optical interconnects is one of the key challenges in the domain of 2.5D/3D electro-optic integration. Enabling high-speed on-chip electro-optic conversion and efficient optical transmission across package/board-level short-reach interconnections can help overcome the limitations of a conventional electrical I/O in terms of bandwidth density and power consumption in a high-performance computing environment. In this context, we have demonstrated a novel optical coupling interface to integrate silicon photonics with board-level optical interconnects. We show that by integrating a ball lens in a via drilled in an organic package substrate, the optical beam diffracted from a downward directionality grating on a photonics chip can be coupled to a board-level polymer multimode waveguide with a good alignment tolerance. A key result from the experiment was a 14 chip-to-package 1-dB lateral alignment tolerance for coupling into a polymer waveguide with a cross-section of 20 x 25. An in-depth analysis of loss distribution across several interfaces was done and a -3.4 dB coupling efficiency was measured between the optical interface comprising of output grating, ball lens and polymer waveguide. Furthermore, it is shown that an efficiency better than -2 dB can be achieved by tweaking few parameters in the coupling interface. The fabrication of the optical interfaces and related measurements are reported and verified with simulation results

3D advanced integration technology for heterogeneous systems

International audience3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description

MEMS Technologies Enabling the Future Wafer Test Systems

As the form factor of microelectronic systems and chips are continuing to shrink, the demand for increased connectivity and functionality shows an unabated rising trend. This is driving the evolution of technologies that requires 3D approaches for the integration of devices and system design. The 3D technology allows higher packing densities as well as shorter chip-to-chip interconnects. Micro-bump technology with through-silicon vias (TSVs) and advances in flip chip technology enable the development and manufacturing of devices at bump pitch of 14 μm or less. Silicon carrier or interposer enabling 3D chip stacking between the chip and the carrier used in packaging may also offer probing solutions by providing a bonding platform or intermediate board for a substrate or a component probe card assembly. Standard vertical probing technologies use microfabrication technologies for probes, templates and substrate-ceramic packages. Fine pitches, below 50 μm bump pitch, pose enormous challenges and microelectromechanical system (MEMS) processes are finding applications in producing springs, probes, carrier or substrate structures. In this chapter, we explore the application of MEMS-based technologies on manufacturing of advanced probe cards for probing dies with various new pad or bump structures

High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Signal and Power Integrity Challenges for High Density System-on-Package

As the increasing desire for more compact, portable devices outpaces Moore’s law, innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself, as the case for system-on-package (SoP), has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining, let alone improving, reliability and performance. The fundamental signal, power, and thermal integrity issues are discussed in detail, along with published techniques from around the industry to mitigate these issues in SoP applications

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Thermal modeling and analysis of advanced 3D stacked structures

AbstractThe emerging three-dimensional integrated circuits (3D ICs) offer a promising solution to mitigate the barriers of interconnect scaling in modern systems. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology exacerbates the on-chip thermal issues and increases packaging and cooling costs. In this work, a 3D thermal model of a stacked system is developed and thermal analysis is performed in order to analyze different workload conditions using finite element simulations. The steady-state heat transfer analysis on the 3D stacked structure has been performed in order to analyze the effect of variation of die power consumption, with and without hotspots, on temperature in different layers of the stack has been analyzed. We have also investigated the effect of the interaction of hotspots has on peak temperature