Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and low-latency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect that is straightforwardly adapted to 3-D integration, the proposed method yields up to (times 2.11) and (times 1.11) improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu–Cu TSV bonding techniques, respectively

Approches d'optimisation et de personnalisation des réseaux sur puce (NoC : Networks on Chip)

Systems-on-chip (SoC) have become more and more complex due to the development of integrated circuit technology.Recent studies have shown that in order to improve the performance of a specific SoC application domain, the on-chipinter-connects (OCI) architecture must be customized at design-time or at run-time. Related approaches generallyprovide application-specific SoCs tailored to specific applications. The aim of this thesis is to carry out new approachesfor Network-on-Chip (NoC) and study their performances, especially in terms of latency, throughput, energyconsumption and simplicity of implementation.We have proposed an approach to allow designers to customize a candidate OCI architecture by adding strategiclinks in order to match large application workload. The analytical evaluation focuses on improving the physicalparameters of the NoC topology regardless of the application that should run on. The evaluation by simulationfocuses to evaluate the communication performances of the NoC. Simulations results show the effectiveness ofthis approach to improve the NoC performances. We have also introduced a compartmental Fluid-flow basedmodeling approach to allocate required resource for each buffer based on the application traffic pattern. Simulationsare conducted and results show the efficiency of this modeling method for a buffer space optimized allocation.Finally, we proposed a joint approach based on a system dynamics theory for evaluating the performance of a flowcontrol algorithm in NoCs. This algorithm allows NoC elements to dynamically adjust their inflow by using afeedback control-based mechanism. Analytical and simulation results showed the viability of this mechanism forcongestion avoidance in NoCs.Les systèmes embarqués sur puce (SoC : Systems-on-Chip) sont devenus de plus en plus complexes grâce à l’évolution de la technologie des circuits intégrés. Des études récentes ont montré que pour améliorer les performances du réseau su puce (NoC : Network-on-Chip), l’architecture de celui-ci pouvait être personnalisée, soit au moment de la conception, soit au moment de l’exécution. L’objectif principal de cette thèse est d’implémenter de nouvelles approches pour améliorer les performances des NoCs, notamment la latence, le débit, la consommation d’énergie, et la simplicité de mise en œuvre.Nous avons proposé une approche pour permettre aux concepteurs de personnaliser l'architecture d’un NoC par insertion de liens stratégiques, pour qu’elle soit adaptée à de nombreuses applications, sous la contrainte d’un budget limité en termes de nombre de liens. L’évaluation analytique porte sur l’amélioration des paramètres physiques de la topologie du NoC sans tenir compte de l’application qui devrait s’exécuter dessus. L’évaluation par simulation porte sur l’évaluation des performances de communication du NoC. Les résultats de simulations montrent l’efficacité de notre approche pour améliorer les performances du NoC. Nous avons également introduit une approche de modélisation par réseau à compartiments pour allouer les ressources nécessaires pour chaque tampon selon le modèle de trafic de l'application cible. Les résultats de simulations montrent l'efficacité de cette approche de modélisation pour l’allocation optimisée de l'espace tampon. Enfin, nous avons proposé une approche conjointe basée sur la théorie des systèmes dynamiques pour évaluer la performance d'un algorithme de contrôle de flux dans les NoCs. Cet algorithme permet aux éléments du NoC d’ajuster dynamiquement leur entrée en utilisant un mécanisme basé sur le contrôle de flux par rétroaction. Les résultats d’évaluations analytiques et de simulation montrent la viabilité de ce mécanisme pour éviter la congestion dans les NoCs

Computing graph neural networks: A survey from algorithms to accelerators

Graph Neural Networks (GNNs) have exploded onto the machine learning scene in recent years owing to their capability to model and learn from graph-structured data. Such an ability has strong implications in a wide variety of fields whose data are inherently relational, for which conventional neural networks do not perform well. Indeed, as recent reviews can attest, research in the area of GNNs has grown rapidly and has lead to the development of a variety of GNN algorithm variants as well as to the exploration of ground-breaking applications in chemistry, neurology, electronics, or communication networks, among others. At the current stage research, however, the efficient processing of GNNs is still an open challenge for several reasons. Besides of their novelty, GNNs are hard to compute due to their dependence on the input graph, their combination of dense and very sparse operations, or the need to scale to huge graphs in some applications. In this context, this article aims to make two main contributions. On the one hand, a review of the field of GNNs is presented from the perspective of computing. This includes a brief tutorial on the GNN fundamentals, an overview of the evolution of the field in the last decade, and a summary of operations carried out in the multiple phases of different GNN algorithm variants. On the other hand, an in-depth analysis of current software and hardware acceleration schemes is provided, from which a hardware-software, graph-aware, and communication-centric vision for GNN accelerators is distilled.This work is possible thanks to funding from the European Union’s Horizon 2020 research and innovation programme under Grant No. 863337 (WiPLASH project) and the Spanish Ministry of Economy and Competitiveness under contract TEC2017-90034-C2-1-R (ALLIANCE project) that receives funding from FEDER.Peer ReviewedPostprint (published version

Resource Allocation for Software Pipelines in Many-core Systems

Many-core systems integrate a growing number of cores on a single chip and are expected to integrate hundreds and even thousands of cores soon. Despite their massive processing power, it is crucial to employ their resources efficiently to benefit from parallel processing. This dissertation tackles a major challenge, resource allocation, for complex, memory-intensive applications. The proposed methods allow to significantly improve the performance over the state of the art in many scenarios