3D IC optimal layout design. A parallel and distributed topological approach

The task of 3D ICs layout design involves the assembly of millions of components taking into account many different requirements and constraints such as topological, wiring or manufacturability ones. It is a NP-hard problem that requires new non-deterministic and heuristic algorithms. Considering the time complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is superior to any other local search method. Nevertheless, it can often miss to reach a quasi-optimal solution in 3D spaces. The presented approach uses an original 3D layout graph partitioning heuristics implemented with use of the extremal optimization method. The goal is to minimize the total wire-length in the chip. In order to improve the time complexity a parallel and distributed Java implementation is applied. Inside one Java Virtual Machine separate optimization algorithms are executed by independent threads. The work may also be shared among different machines by means of The Java Remote Method Invocation system.Comment: 26 pages, 9 figure

Optimized Surface Code Communication in Superconducting Quantum Computers

Quantum computing (QC) is at the cusp of a revolution. Machines with 100 quantum bits (qubits) are anticipated to be operational by 2020 [googlemachine,gambetta2015building], and several-hundred-qubit machines are around the corner. Machines of this scale have the capacity to demonstrate quantum supremacy, the tipping point where QC is faster than the fastest classical alternative for a particular problem. Because error correction techniques will be central to QC and will be the most expensive component of quantum computation, choosing the lowest-overhead error correction scheme is critical to overall QC success. This paper evaluates two established quantum error correction codes---planar and double-defect surface codes---using a set of compilation, scheduling and network simulation tools. In considering scalable methods for optimizing both codes, we do so in the context of a full microarchitectural and compiler analysis. Contrary to previous predictions, we find that the simpler planar codes are sometimes more favorable for implementation on superconducting quantum computers, especially under conditions of high communication congestion.Comment: 14 pages, 9 figures, The 50th Annual IEEE/ACM International Symposium on Microarchitectur

Designing heterogeneous porous tissue scaffolds for additive manufacturing processes

A novel tissue scaffold design technique has been proposed with controllable heterogeneous architecture design suitable for additive manufacturing processes. The proposed layer-based design uses a bi-layer pattern of radial and spiral layers consecutively to generate functionally gradient porosity, which follows the geometry of the scaffold. The proposed approach constructs the medial region from the medial axis of each corresponding layer, which represents the geometric internal feature or the spine. The radial layers of the scaffold are then generated by connecting the boundaries of the medial region and the layer's outer contour. To avoid the twisting of the internal channels, reorientation and relaxation techniques are introduced to establish the point matching of ruling lines. An optimization algorithm is developed to construct sub-regions from these ruling lines. Gradient porosity is changed between the medial region and the layer's outer contour. Iso-porosity regions are determined by dividing the subregions peripherally into pore cells and consecutive iso-porosity curves are generated using the isopoints from those pore cells. The combination of consecutive layers generates the pore cells with desired pore sizes. To ensure the fabrication of the designed scaffolds, the generated contours are optimized for a continuous, interconnected, and smooth deposition path-planning. A continuous zig-zag pattern deposition path crossing through the medial region is used for the initial layer and a biarc fitted isoporosity curve is generated for the consecutive layer with C-1 continuity. The proposed methodologies can generate the structure with gradient (linear or non-linear), variational or constant porosity that can provide localized control of variational porosity along the scaffold architecture. The designed porous structures can be fabricated using additive manufacturing processes

Multi-Objective Design Optimization of the Reinforced Composite Roof in a Solar Vehicle

Abstract: A multi-step and -objective design approach was used to optimize the photovoltaic roof in a multi-occupant racing vehicle. It permitted to select the best combination of design features (as shapes, widths, angles) in composite structures simultaneously balancing opposite requirements as static strength and dynamic stiffness. An attention to functional requirements, as weight, solar cells cooling and solar energy conversion, was also essential. Alternative carbon fiber-reinforced plastic structures were investigated by finite elements using static and modal analyses in the way to compare several design configurations in terms of natural frequencies, deformations, flexural stiffness, torsional stiffness, and heat exchange surfaces. A representative roof section was manufactured and tested for model validation. A significant improvement respect to the pre-existing solar roof was detected. The final configuration was manufactured and installed on the vehicle

Using graphical style and visibility constraints for a meaningful layout in visual programming interfaces

In the expanding field of visual applications, layout design and graphical editing tasks are crucial points. In this paper, we address the incorporation of AI aspects in the visual software design process and the automatic layout and beautification of informational graphics such as visual programs and chart diagrams. Since layout in dynamic settings frequently requires a direct manipulation responsiveness, an incremental redesign of the generated visual material is necessary. Following our previous work on constraint-based multimodal design, we show how powerful constraint processing techniques, such as constraint hierarchies and dynamic constraint satisfaction, can be applied to visual programming environments in order to maintain graphical style and consistency for a meaningful layout. We describe InLay, a system for constraint-based presenting and editing visual programs. Finally, we will have a short look at some extensions with regard to advanced interaction and visualization techniques

Practical Techniques for Improving Performance and Evaluating Security on Circuit Designs

As the modern semiconductor technology approaches to nanometer era, integrated circuits (ICs) are facing more and more challenges in meeting performance demand and security. With the expansion of markets in mobile and consumer electronics, the increasing demands require much faster delivery of reliable and secure IC products. In order to improve the performance and evaluate the security of emerging circuits, we present three practical techniques on approximate computing, split manufacturing and analog layout automation. Approximate computing is a promising approach for low-power IC design. Although a few accuracy-configurable adder (ACA) designs have been developed in the past, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. We investigate a simple ACA design that contains no redundancy or error detection/correction circuitry and uses very simple carry prediction. The simulation results show that our design dominates the latest previous work on accuracy-delay-power tradeoff while using 39% less area. One variant of this design provides finer-grained and larger tunability than that of the previous works. Moreover, we propose a delay-adaptive self-configuration technique to further improve the accuracy-delay-power tradeoff. Split manufacturing prevents attacks from an untrusted foundry. The untrusted foundry has front-end-of-line (FEOL) layout and the original circuit netlist and attempts to identify critical components on the layout for Trojan insertion. Although defense methods for this scenario have been developed, the corresponding attack technique is not well explored. Hence, the defense methods are mostly evaluated with the k-security metric without actual attacks. We develop a new attack technique based on structural pattern matching. Experimental comparison with existing attack shows that the new attack technique achieves about the same success rate with much faster speed for cases without the k-security defense, and has a much better success rate at the same runtime for cases with the k-security defense. The results offer an alternative and practical interpretation for k-security in split manufacturing. Analog layout automation is still far behind its digital counterpart. We develop the layout automation framework for analog/mixed-signal ICs. A hierarchical layout synthesis flow which works in bottom-up manner is presented. To ensure the qualified layouts for better circuit performance, we use the constraint-driven placement and routing methodology which employs the expert knowledge via design constraints. The constraint-driven placement uses simulated annealing process to find the optimal solution. The packing represented by sequence pairs and constraint graphs can simultaneously handle different kinds of placement constraints. The constraint-driven routing consists of two stages, integer linear programming (ILP) based global routing and sequential detailed routing. The experiment results demonstrate that our flow can handle complicated hierarchical designs with multiple design constraints. Furthermore, the placement performance can be further improved by using mixed-size block placement which works on large blocks in priority