Modeling of a carbon nanotube sensing device

A sensing device is modeled and discussed in this paper. The modeling is done by using carbon nanotubes. This carbon nanotube based sensing device makes it possible produce huge amount of nano chips as a disposable cartridge for diagnostic purposes. Modeling of nano-electrode, characterization and electrochemical detection of DNA hybridization is discussed here. The results shows that the importance of diagnostics with demonstrated characteristics of high sensitivity, reliability and inexpensive micro-fabrication for cost effectiveness

Smart energy management and conversion

This chapter introduced power management circuits and energy storage unit designs for sub‐1 mW low power energy harvesting technologies, including indoor light energy harvesting, thermoelectric energy harvesting and vibration energy harvesting. The solutions address several of the problems associated with energy harvesting, power management and storage issues including low voltage operation, self‐start, efficiency (conversion efficiency as well as impact of power consumption of the power management circuit itself), energy density and leakage current levels. Additionally, efforts to miniaturize and integrate magnetic parts as well as integrate discrete circuits onto silicon are outlined to offer improvements in cost, size and efficiency. Finally initial results from efforts to improve energy density of storage devices using nanomaterials are introduced

An Outlook on Design Technologies for Future Integrated Systems

The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is paving the way to a new class of heterogeneous integrated systems, with increased performance and connectedness and providing us with gateways to the living world. This paper surveys design requirements and solutions for heterogeneous systems and addresses design technologies for realizing them

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon NanoWire FET (SiNWFET), is being introduced by the research community. These devices keep on pursuing Mooreâs Law by improving channel electrostatic controllability, thereby reducing the Off âstate leakage current. In addition to these improvements, recent developments introduced devices with enhanced capabilities, such as Controllable-Polarity (CP) SiNWFETs, which make them very interesting for compact logic cell and arithmetic circuits. At advanced technology nodes, the amount of physical controls, during the fabrication process of nanometer devices, cannot be precisely determined because of technology fluctuations. Consequently, the structural parameters of fabricated circuits can be significantly different from their nominal values. Moreover, giving an a-priori conclusion on the variability of advanced technologies for emerging nanoscale devices, is a difficult task and novel estimation methodologies are required. This is a necessity to guarantee the performance and the reliability of future integrated circuits. Statistical analysis of process variation requires a great amount of numerical data for nanoscale devices. This introduces a serious challenge for variability analysis of emerging technologies due to the lack of fast simulation models. One the one hand, the development of accurate compact models entails numerous tests and costly measurements on fabricated devices. On the other hand, Technology Computer Aided Design (TCAD) simulations, that can provide precise information about devices behavior, are too slow to timely generate large enough data set. In this research, a fast methodology for generating data set for variability analysis is introduced. This methodology combines the TCAD simulations with a learning algorithm to alleviate the time complexity of data set generation. Another formidable challenge for variability analysis of the large circuits is growing number of process variation sources. Utilizing parameterized models is becoming a necessity for chip design and verification. However, the high dimensionality of parameter space imposes a serious problem. Unfortunately, the available dimensionality reduction techniques cannot be employed for three main reasons of lack of accuracy, distribution dependency of the data points, and finally incompatibility with device and circuit simulators. We propose a novel technique of parameter selection for modeling process and performance variation. The proposed technique efficiently addresses the aforementioned problems. Appropriate testing, to capture manufacturing defects, plays an important role on the quality of integrated circuits. Compared to conventional CMOS, emerging nano-devices such as CP-SiNWFETs have different fabrication process steps. In this case, current fault models must be extended for defect detection. In this research, we extracted the possible fabrication defects, and then proposed a fault model for this technology. We also provided a couple of test methods for detecting the manufacturing defects in various types of CP-SiNWFET logic gates. Finally, we used the obtained fault model to build fault tolerant arithmetic circuits with a bunch of superior properties compared to their competitors

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Interrogation of Single Asperity Electrical Contacts Using atomic force Microscopy With Application to Nems Logic Switches

Energy consumption by computers and electronics is currently 15% of worldwide energy output, and growing. Aggressive scaling of the fully-electronic transistor, which is the fundamental computational element of these devices, has led to significant and immutable energy losses. Ohmic nanoelectromechanical systems (NEMS) logic switches have been recognized as a potential transistor replacement technology with projected energy savings of one to three orders of magnitude over traditional, fully-electronic transistors. However, the use of conventional, adhesive contact materials (i.e. metals) in NEMS switches electrical contacts leads to permanent device seizure or the formation of insulating tribofilms that inhibits commercialization of this technology. Of critical need is a method to efficiently identify and interrogate low adhesion, chemically stable electrical contact material pairs under conditions and scales relevant to NEMS logic switch contacts. This thesis presents the development of two electrical contact testing methods based on atomic force microscopy (AFM) to interrogate electrical contact materials under contact forces and environments representative of NEMS logic switch operating conditions. AFM was used to mimic the interaction of Pt/Pt NEMS logic switch electrical interfaces for up to two billion contact cycles in laboratory timeframes. Contact resistance before cycling significantly exceeded theoretical predictions for clean Pt/Pt interfaces due to adsorbed contaminant films and increased up to six orders of magnitude due to cycling-induced insulating tribopolymer growth. Sliding of the contact with microscale amplitudes lead to significant recovery of conductivity through displacement of the insulating films. Based on this observation, AFM was then used to investigate the role of load, shear, electrical bias, and environment on the electrical robustness of Pt/nitrogen-incorporated ultrananocrystalline diamond (N-UNCD) and Pt/Pt interfaces. N-UNCD was selected because similar diamond films have demonstrated low adhesion, chemical inertness, and compatibility with NEMS logic device fabrication. Pt/N-UNCD interfaces subjected to low loads during sliding demonstrated significant increases in contact resistance due to insulating film formation that was not observed at larger loads. Taken in concert, these finding demonstrate the capability of AFM to investigate nanoscale electrical contact phenomena without the need for time-consuming and expensive integration of unproven materials in NEMS logic switches