A Case Study in CMOS Design Scaling for Analog Applications: The Ringamp LDO

As CMOS process nodes scale to smaller feature sizes, process optimizations are made to achieve improvements in digital circuit performance, such as increasing speed and memory, while decreasing power consumption. Unfortunately for analog design, these optimizations usually come at the expense of poorer transistor performance, such as reduced small signal output resistance and increased channel length modulation. The ring amplifier has been proposed as a digital solution to the analog scaling problem, by configuring digital inverters to function as analog amplifiers through deadzone biasing. As digital inverters naturally scale, the ring amplifier is a promising area of exploration for analog design. This work presents a ring amplifier scaling study by demonstration of scaling an output capacitor-less, ring amplifier based low-dropout voltage regulator designed in a standard 180 nm CMOS process down to a standard 90 nm CMOS process

Design methodology for reliable and energy efficient self-tuned on-chip voltage regulators

The energy-efficiency needs in computing systems, ranging from high performance processors to low-power devices is steadily on the rise, resulting in increasing popularity of on-chip voltage regulators (VR). The high-frequency and high bandwidth on-chip voltage regulators such as Inductive voltage regulators (IVR) and Digital Low Dropout regulators (DLDO) significantly enhance the energy-efficiency of a SoC by reducing supply noise and enabling faster voltage transitions. However, IVRs and DLDOs need to cope with the higher variability that exists in the deep nanometer digital nodes since they are fabricated on the same die as the digital core affecting performance of both the VR and digital core. Moreover, in most modern SoCs where multiple power domains are preferred, each VR needs to be designed and optimized for a target load demand which significantly increases the design time and time to market for VR assisted SoCs. This thesis investigates a performance-based auto-tuning algorithm utilizing performance of digital core to tune VRs against variations and improve performance of both VR and the core. We further propose a fully synthesizable VR architecture and an auto-generation tool flow that can be used to design and optimize a VR for given target specifications and auto-generate a GDS layout. This would reduce the design time drastically. And finally, a flexible precision IVR architecture is also explored to further improve transient performance and tolerance to process variations. The proposed IVR and DLDO designs with an AES core and auto-tuning circuits are prototyped in two testchips in 130nm CMOS process and one test chip in 65nm CMOS process. The measurements demonstrate improved performance of IVR and AES core due to performance-based auto-tuning. Moreover, the synthesizable architectures of IVR and DLDO implemented using auto-generation tool flow showed competitive performance with state of art full custom designs with orders of magnitude reduction in design time. Additional improvement in transient performance of IVR is also observed due to the flexible precision feedback loop design.Ph.D

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Bulk-micromachined mass airflow sensor fabrication and testing methodology for an undergraduate microfabrication course.

In July 1995, National Science Foundation Award # 9551869 funded the development of a new inter-disciplinary microfabrication course under the primary leadership of Dr. Kevin Walsh at the University of Louisville. Along with this award, the completed construction of a new building in 1996 that contained a class 1000/100 cleanroom laboratory facilitated the development of the course. Moreover, curricula had to be completed to provide students with practical, hands-on experience in building Micro Electro-Mechanical Systems (MEMS) devices using processes and methodologies introduced in the course. Dr. Walsh wanted to include a mass airflow sensor in his portfolio of total possible devices students could build in the cleanroom lab for the course. This document describes the design of a bulk-micromachined, monolithic, mass airflow sensor with a thermally-isolated, thin-film, dielectric, microbridge/diaphragm design. In addition, several fabrication methodologies were explored, as well as a means to test and evaluate the sensors for this undergraduate class laboratory. The mass airflow sensor architecture chosen was based upon a closed-loop-control,microelectronic thermal (hot-wire) anemometer design, which was first developed and presented by Johnson, Higashi, et. al. at Honeywell in the mid 1980s [2]. Two separate photomask sets were developed using L-Edit™ software (by Tanner Research), with each set including multiple geometric variations of a dual/triple microbridge/cantilever flow sensor structure to be suspended over a precision, anisotropically-etched pit, integrated onto a (100) silicon substrate. Four primary structural fabrication strategies were explored to produce the thin-film material for the flow sensors: (1) RF planar magnetron sputter-deposited 1 m m -thick silicon nitride microbridges/cantilevers; (2) anodically-bonded-and-machined 20-30 m m -thick borosilicate glass diaphragms; (3) spin-on-glass microbridges/cantilevers; and (4) low-stress, 0.5 m m -thick, LPCVD silicon nitride microbridges/cantilevers. Four resistor metallizations were separately evaluated: permalloy (Ni81Fe19), chromium, titanium, and platinum. A process was developed and documented to successfully fabricate flow sensors with low stress LPCVD silicon nitride microbridges/cantilevers. DC planar magnetron sputterdeposited platinum thin-film resistors (with a ~120 nm-thick RF planar magnetron sputterdeposited chromium adhesion layer), with nominal thicknesses of ~56 – 70 nm, were delineated by photolithographic imaging techniques. The resistors had measured Temperature Coefficients of Resistance (TCR) in the range of 1.93 – 2.25 x10-3 W /W /°C at 25 - 125 °C. Anisotropic KOH etching of the (100)-oriented silicon substrate was utilized to release the flow sensor microbridge/cantilever microstructures. After designing and building a flow sensor test machine capable of controlled volumetric air flow rates of up to ~15 SLPM (0.54 m/s), nominal sensor sensitivities (SV) of up to 0.67 mV/SLPM (20.4 mV/(m/s)) were measured. The sensitivities varied somewhat depending upon resistor values set in the flow sensor heater-driver circuit and the insertion depth of the devices within the flow channel

A History of Materials and Technologies Development

The purpose of the book is to provide the students with the text that presents an introductory knowledge about the development of materials and technologies and includes the most commonly available information on human development. The idea of the publication has been generated referring to the materials taken from the organic and non-organic evolution of nature. The suggested texts might be found a purposeful tool for the University students proceeding with studying engineering due to the fact that all subjects in this particular field more or less have to cover the history and development of the studied object. It is expected that studying different materials and technologies will help the students with a better understanding of driving forces, positive and negative consequences of technological development, etc

Proceedings of the 19th Sound and Music Computing Conference

Proceedings of the 19th Sound and Music Computing Conference - June 5-12, 2022 - Saint-Étienne (France). https://smc22.grame.f

The 2nd International Electronic Conference on Applied Sciences

This book is focused on the works presented at the 2nd International Electronic Conference on Applied Sciences, organized by Applied Sciences from 15 to 31 October 2021 on the MDPI Sciforum platform. Two decades have passed since the start of the 21st century. The development of sciences and technologies is growing ever faster today than in the previous century. The field of science is expanding, and the structure of science is becoming ever richer. Because of this expansion and fine structure growth, researchers may lose themselves in the deep forest of the ever-increasing frontiers and sub-fields being created. This international conference on the Applied Sciences was started to help scientists conduct their own research into the growth of these frontiers by breaking down barriers and connecting the many sub-fields to cut through this vast forest. These functions will allow researchers to see these frontiers and their surrounding (or quite distant) fields and sub-fields, and give them the opportunity to incubate and develop their knowledge even further with the aid of this multi-dimensional network

NOTIFICATION !!!

All the content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition