Three Highly Parallel Computer Architectures and Their Suitability for Three Representative Artificial Intelligence Problems

Virtually all current Artificial Intelligence (AI) applications are designed to run on sequential (von Neumann) computer architectures. As a result, current systems do not scale up. As knowledge is added to these systems, a point is reached where their performance quickly degrades. The performance of a von Neumann machine is limited by the bandwidth between memory and processor (the von Neumann bottleneck). The bottleneck is avoided by distributing the processing power across the memory of the computer. In this scheme the memory becomes the processor (a smart memory ). This paper highlights the relationship between three representative AI application domains, namely knowledge representation, rule-based expert systems, and vision, and their parallel hardware realizations. Three machines, covering a wide range of fundamental properties of parallel processors, namely module granularity, concurrency control, and communication geometry, are reviewed: the Connection Machine (a fine-grained SIMD hypercube), DADO (a medium-grained MIMD/SIMD/MSIMD tree-machine), and the Butterfly (a coarse-grained MIMD Butterflyswitch machine)

An analysis of interconnection network effects of dynamic element matching digital-to-analog converters

Digital-to-Analog Converters (DACs) convert digital signals into analog signals and thereby provide the link from digital systems to the analog world. Many DAC architectures use matched components to convert signals. However, practical DACs contain mismatched circuit components that cause nonlinear errors in the DAC\u27s analog output signal. Dynamic Element Matching (DEM) is a method that can eliminate or reduce the effects of mismatch errors. In this thesis, DEM algorithms applied to a specific DEM DAC architecture that use several interconnection networks, including the Barrel Shifting network, the Generalized-Cube network, the Omega network and the Indirect Binary n-cube network, are mathematically analyzed. The hardware complexity of some networks is discussed and a new interconnection network is developed and is shown to be hardware efficient when applied to the specific DEM DAC architecture

Graph Algorithms on GPUs

This chapter introduces the topic of graph algorithms on GPUs. It starts by presenting and comparing the main important data structures and techniques applied for representing and analysing graphs on GPUs at the state of the art.It then presents the theory and an updated review of the most efficient implementations of graph algorithms for GPUs. In particular, the chapter focuses on graph traversal algorithms (breadth-first search), single-source shortest path(Djikstra, Bellman-Ford, delta stepping, hybrids), and all-pair shortest path (Floyd-Warshall). By the end of the chapter, load balancing and memory access techniques are discussed through an overview of their main issues and management techniques