A Flexible Approach for Smart Management of Transmissions in Power Line Communications

Power line communications (PLCs) refer to a technology based on the existing electrical wiring to transmit data among the devices connected to the network. The PLC technology is an excellent solution widely studied and analysed by researchers, even in those areas characterized by strict requirements, such as industries. In this paper, a technique based on fuzzy logic, for the dynamic management of the amplitude of the signal emitted by the devices of a power line network, is proposed. The main aim is to manage the amplitude of the transmission signal in order to reduce the noise introduced into the network, and, as a consequence, the power consumption, increasing data transmission quality of network in terms of Quality of Service (QoS). This solution has been implemented into embedded systems based on the ADD1010, a power line System on Chip (SoC), and tested through a real scenario realized in laboratory

On the Exploitation of a High-throughput SHA-256 FPGA Design for HMAC

High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board)

Étude et modélisation des structures de transmission non uniformes : applications à l'adaptation d'impédance et au filtrage

Le but de ce travail est d'exposer l'utilité des lignes non uniformes pour compenser des non linéarités avec une approche physique orientée vers la conception des circuits micro-ondes. En effet, certaines structures de transmission non uniformes bien choisis, peuvent, grâce à leur comportement fréquentiel compenser des parasites harmoniques dans des circuits passifs microondes et aussi une non linéarité dans les circuits actifs. Il suffit pour cela de bien choisir la loi de non uniformité afin de maîtriser une non linéarité connue. Ce travail exposera le cas des lignes de transmission non uniformes conçues et réalisées en technologie microbande (stripline). La première partie, purement théorique, décrit une méthode originale de modélisation de ces lignes de transmission non uniformes quelque soit leur profil de non homogénéité. Cette méthode nous permet, suite à l'identification à une équation de Hill, de l'équation régissant le problème physique à traiter de résoudre des problèmes de propagation électromagnétique en milieu hétérogène. Son originalité est de fournir une expression analytique générale et explicite de la solution sous la forme d'un développement en série de Fourier, mieux adapté qu'un résultat purement numérique caril confère un sens physique au problème considéré. La deuxième partie, consistera à définir de manière objective les lignes de transmission non uniformes et à étudier leur comportement fréquentiel ainsi que la différence qu'elles présentent par rapport aux structures de transmissions uniformes classiques. La dernière partie présente des applications originales de ces lignes dans la réduction des harmoniques parasites générés par des dispositifs passifs ainsi que l'amélioration des circuits actifs en ce qui concerne la présence des harmoniques dans le signal de sortie

Platform-based design, test and fast verification flow for mixed-signal systems on chip

This research is providing methodologies to enhance the design phase from architectural space exploration and system study to verification of the whole mixed-signal system. At the beginning of the work, some innovative digital IPs have been designed to develop efficient signal conditioning for sensor systems on-chip that has been included in commercial products. After this phase, the main focus has been addressed to the creation of a re-usable and versatile test of the device after the tape-out which is close to become one of the major cost factor for ICs companies, strongly linking it to model’s test-benches to avoid re-design phases and multi-environment scenarios, producing a very effective approach to a single, fast and reliable multi-level verification environment. All these works generated different publications in scientific literature. The compound scenario concerning the development of sensor systems is presented in Chapter 1, together with an overview of the related market with a particular focus on the latest MEMS and MOEMS technology devices, and their applications in various segments. Chapter 2 introduces the state of the art for sensor interfaces: the generic sensor interface concept (based on sharing the same electronics among similar applications achieving cost saving at the expense of area and performance loss) versus the Platform Based Design methodology, which overcomes the drawbacks of the classic solution by keeping the generality at the highest design layers and customizing the platform for a target sensor achieving optimized performances. An evolution of Platform Based Design achieved by implementation into silicon of the ISIF (Intelligent Sensor InterFace) platform is therefore presented. ISIF is a highly configurable mixed-signal chip which allows designers to perform an effective design space exploration and to evaluate directly on silicon the system performances avoiding the critical and time consuming analysis required by standard platform based approach. In chapter 3 we describe the design of a smart sensor interface for conditioning next generation MOEMS. The adoption of a new, high performance and high integrated technology allow us to integrate not only a versatile platform but also a powerful ARM processor and various IPs providing the possibility to use the platform not only as a conditioning platform but also as a processing unit for the application. In this chapter a description of the various blocks is given, with a particular emphasis on the IP developed in order to grant the highest grade of flexibility with the minimum area occupation. The architectural space evaluation and the application prototyping with ISIF has enabled an effective, rapid and low risk development of a new high performance platform achieving a flexible sensor system for MEMS and MOEMS monitoring and conditioning. The platform has been design to cover very challenging test-benches, like a laser-based projector device. In this way the platform will not only be able to effectively handle the sensor but also all the system that can be built around it, reducing the needed for further electronics and resulting in an efficient test bench for the algorithm developed to drive the system. The high costs in ASIC development are mainly related to re-design phases because of missing complete top-level tests. Analog and digital parts design flows are separately verified. Starting from these considerations, in the last chapter a complete test environment for complex mixed-signal chips is presented. A semi-automatic VHDL-AMS flow to provide totally matching top-level is described and then, an evolution for fast self-checking test development for both model and real chip verification is proposed. By the introduction of a Python interface, the designer can easily perform interactive tests to cover all the features verification (e.g. calibration and trimming) into the design phase and check them all with the same environment on the real chip after the tape-out. This strategy has been tested on a consumer 3D-gyro for consumer application, in collaboration with SensorDynamics AG

Uma referência de tensão CMOS baseada na tensão threshold em ultra-baixa tensão e ultra baixa potência.

Esse trabalho apresenta uma nova e simples topologia de referência de tensão threshold, a qual é análoga a uma referência de tensão bandgap. Esse circuito possui a vantagem de operar com uma tensão de alimentação menor do que 1V; além do limite imposto pela tensão de banda proibida (tensão bandgap). A tensão de referência é baseada na tensão de limiar (tensão threshold) de um transistor nMOS em inversão fraca. A tensão de alimentação dos novos processos CMOS 0,13μm e/ou 90nm já é menor do que a tensão bandgap do silício; fato que nunca irá ocorrer com a tensão threshold do transistor MOS. A referência de tensão threshold pode ser utilizada em aplicações típicas de referências de tensão ou mesmo no rastreamento da tensão threshold aplicada na polarização adaptativa de circuitos, por ser uma estrutura que tende a ser insensível a variação na temperatura e na tensão de alimentação. O circuito foi fabricado utilizando o processo CMOS TSMC 0,35μm padrão, gerando uma referência de tensão de 741mV para a tensão de alimentação de 950mV com um consumo de apenas 390nW. O circuito apresenta uma regulação de linha de 25mV/V para uma tensão de alimentação de até 3V e uma variação de 39ppm/°C na tensão de referência para uma faixa de variação na temperatura de – 20°C a + 80°C

An investigation into adaptive power reduction techniques for neural hardware

In light of the growing applicability of Artificial Neural Network (ANN) in the signal processing field [1] and the present thrust of the semiconductor industry towards lowpower SOCs for mobile devices [2], the power consumption of ANN hardware has become a very important implementation issue. Adaptability is a powerful and useful feature of neural networks. All current approaches for low-power ANN hardware techniques are ‘non-adaptive’ with respect to the power consumption of the network (i.e. power-reduction is not an objective of the adaptation/learning process). In the research work presented in this thesis, investigations on possible adaptive power reduction techniques have been carried out, which attempt to exploit the adaptability of neural networks in order to reduce the power consumption. Three separate approaches for such adaptive power reduction are proposed: adaptation of size, adaptation of network weights and adaptation of calculation precision. Initial case studies exhibit promising results with significantpower reduction

Optimisation, Optimal Control and Nonlinear Dynamics in Electrical Power, Energy Storage and Renewable Energy Systems

The electrical power system is undergoing a revolution enabled by advances in telecommunications, computer hardware and software, measurement, metering systems, IoT, and power electronics. Furthermore, the increasing integration of intermittent renewable energy sources, energy storage devices, and electric vehicles and the drive for energy efficiency have pushed power systems to modernise and adopt new technologies. The resulting smart grid is characterised, in part, by a bi-directional flow of energy and information. The evolution of the power grid, as well as its interconnection with energy storage systems and renewable energy sources, has created new opportunities for optimising not only their techno-economic aspects at the planning stages but also their control and operation. However, new challenges emerge in the optimization of these systems due to their complexity and nonlinear dynamic behaviour as well as the uncertainties involved.This volume is a selection of 20 papers carefully made by the editors from the MDPI topic “Optimisation, Optimal Control and Nonlinear Dynamics in Electrical Power, Energy Storage and Renewable Energy Systems”, which was closed in April 2022. The selected papers address the above challenges and exemplify the significant benefits that optimisation and nonlinear control techniques can bring to modern power and energy systems