Cmos Rotary Traveling Wave Oscillators (Rtwos)

Rotary Traveling Wave Oscillator (RTWO) represents a transmission line based technology for multi-gigahertz multiple phase clock generation. RTWO is known for providing low jitter and low phase noise signals but the issue of high power consumption is a major drawback in its application. Direction of wave propagation is random and is determined by the least resistance path in the absence of an external direction control circuit. The objective of this research is to address some of the problems of RTWO design, including high power consumption, uncertainty of propagation direction and optimization of design variables. Included is the modeling of RTWO for sensitivity, phase noise and power analysis. Research objectives were met through design, simulation and implementation. Different designs of RTWO in terms of ring size and number of amplifier stages were implemented and tested. Design tools employed include Agilent ADS, Cadence EDA, SONNET and Altium PCB Designer. Test chip was fabricated using IBM 0.18 μm RF CMOS technology. Performance measures of interest are tuning range, phase noise and power consumption. Agilent ADS and SONNET were used for electromagnetic modeling of transmission lines and electromagnetic field radiation. For each design, electromagnetic simulations were carried out followed by oscillation synthesis based on circuit simulation in Cadence Spectre. RTWO frequencies between 2 GHz and 12 GHz were measured based on the ring size of transmission lines. Simulated microstrip transmission line segments had a quality factor between 5.5 and 18. For the various designs, power consumption ranged from 20 mW to 120 mW. Measured phase noise ranged between -123 dBc/Hz and -87 dBc/Hz at 1 MHz offset. Development also included the design of a wide band buffer and a printed circuit board with high signal integrity for accurate measurement of oscillation frequency and other performance measures. Simulated performance, schematics and measurement results are presented

Design considerations for a monolithic, GaAs, dual-mode, QPSK/QASK, high-throughput rate transceiver

A monolithic, GaAs, dual mode, quadrature amplitude shift keying and quadrature phase shift keying transceiver with one and two billion bits per second data rate is being considered to achieve a low power, small and ultra high speed communication system for satellite as well as terrestrial purposes. Recent GaAs integrated circuit achievements are surveyed and their constituent device types are evaluated. Design considerations, on an elemental level, of the entire modem are further included for monolithic realization with practical fabrication techniques. Numerous device types, with practical monolithic compatability, are used in the design of functional blocks with sufficient performances for realization of the transceiver

Green on-chip inductors in three-dimensional integrated circuits

This thesis focuses on the technique for the improvement of quality factor and inductance of the TSV inductors and then on the utilization of TSV inductors in various on-chip applications such as DC-DC converter and resonant clocking. Through-silicon-vias (TSVs) are the enabling technique for three-dimensional integrated circuits (3D ICs). However, their large area significantly reduces the benefits that can be obtained by 3D ICs. On the other hand, a major limiting factor for the implementation of many on-chip circuits such as DC-DC converters and resonant clocking is the large area overhead induced by spiral inductors. Several works have been proposed in the literature to make inductors out of idle TSVs. In this thesis, the technique to improve the quality factor and inductance is proposed and then discusses about two applications utilizing TSV inductors i.e., inductive DC-DC converters and LC resonant clocking. The TSV inductor performs inferior to spiral inductors due to its increases losses. Hence to improve the performance of the TSV inductor, the losses should be reduced. Inductive DC-DC converters become prominent for on-chip voltage conversion because of their high efficiency compared with other types of converters (e.g. linear and capacitive converters). On the other hand, to reduce on-chip power, LC resonant clocking has become an attractive option due to its same amplitude and phases compared to other resonant clocking methods such as standing wave and rotary wave. A major challenge for both applications is associated with the required inductor area. In this thesis, the effectiveness of such TSV inductors in addressing both challenges are demonstrated --Abstract, page iv

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e TecnologiaSignal amplification is required in almost every analog electronic system. However noise is also present, thus imposing limits to the overall circuit performance, e.g., on the sensitivity of the radio transceiver. This drawback has triggered a major research on the field, which has been producing several solutions to achieve amplification with minimum added noise. During the Fifties, an interesting out of mainstream path was followed which was based on variable reactance instead of resistance based amplifiers. The principle of these parametric circuits permits to achieve low noise amplifiers since the controlled variations of pure reactance elements is intrinsically noiseless. The amplification is based on a mixing effect which enables energy transfer from an AC pump source to other related signal frequencies. While the first implementations of these type of amplifiers were already available at that time, the discrete-time version only became visible more recently. This discrete-time version is a promising technique since it is well adapted to the mainstream nanoscale CMOS technology. The technique itself is based on the principle of changing the surface potential of the MOS device while maintaining the transistor gate in a floating state. In order words, the voltage amplification is achieved by changing the capacitance value while maintaining the total charge unchanged during an amplification phase. Since a parametric amplifier is not intrinsically dependent on the transconductance of the MOS transistor, it does not directly suffer from the intrinsic transconductance MOS gain issues verified in nanoscale MOS technologies. As a consequence, open-loop and opamp free structures can further emerge with this additional contribution. This thesis is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. The use of the latter is supported on the presentation of several circuits where the MOS Parametric Amplifier cell is well suited: small gain amplifier, comparator, discrete-time mixer and filter, and ADC. Relatively to the latter, a high speed time-interleaved pipeline ADC prototype is implemented in a,standard 130 nm CMOS digital technology from United Microelectronics Corporation (UMC). The ADC is fully based on parametric MOS amplification which means that one could achieve a compact and MOS-only implementation. Furthermore, any high speed opamp has not been used in the signal path, being all the amplification steps implemented with open-loop parametric MOS amplifiers. To the author’s knowledge, this is first reported pipeline ADC that extensively used the parametric amplification concept.Fundação para a Ciência e Tecnologia through the projects SPEED, LEADER and IMPAC

Low Power Resonant Rotary Global Clock Distribution Network Design

Along with the increasing complexity of the modern very large scale integrated (VLSI) circuit design, the power consumption of the clock distribution network in digital integrated circuits is continuously increasing. In terms of power and clock skew, the resonant clock distribution network has been studied as a promising alternative to the conventional clock distribution network. Resonant clock distribution network, which works based on adiabatic switching principles, provides a complete solution for on-chip clock generation and distribution for low-power and low-skew clock network designs for high-performance synchronous VLSI circuits.This dissertation work aims to develop the global clock distribution network for one kind of resonant clocking technologies: The resonant rotary clocking technology. The following critical aspects are addressed in this work: (1) A novel rotary oscillator array (ROA) topology is proposed to solve the signal rotation direction uniformity problem, in order to support the design of resonant rotary clocking based low-skew clock distribution network; (2) A synchronization scheme is proposed to solve the large scale rotary clocking generation circuit synchronization problem; (3) A low-skew rotary clock distribution network design methodology is proposed with frequency, power and skew optimizations; (4) A resonant rotary clocking based physical design flow is proposed, which can be integrated in the current mainstream IC design flow; (5) A dynamic rotary frequency divider is proposed for dynamic frequency scaling applications. Experimental and theoretical results show: (1) The efficiency of the proposed methodology in the construction of low-skew, low-power resonant rotary clock distribution network. (2) The effectiveness of the dynamic rotary frequency divider in extending the operating frequency range of the low-power resonant rotary based applications.Ph.D., Electrical Engineering -- Drexel University, 201

Ku band rotary traveling-wave voltage controlled oscillator

Voltage-controlled oscillator (VCO) plays a key role in determination of the link budget of wireless communication, and consequently the performance of the transceiver. Lowering the noise contribution from the VCO to the entire system is always challenging and remains the active research area. Motivated by high demands for the low-phase noise, low-power consumption VCO in the application of 5G, radar-sensing system, implantable device, to name a few, this research focused on the design of a rotary travelling-wave oscillator (RTWO). A power conscious RTWO with reliable direction control of the wave propagation was investigated. The phase noise was analyzed based on the proposed RTWO. The phase noise reduction technique was introduced by using tail current source filtering technique in which a figure-8 inductors were employed. Three RTWO were implemented based on GF 130 nm standard CMOS process and TSMC 130 nm standard CMOS process. The first design was achieving 16-GHz frequency with power consumption of 5.8-mW with 190.3 dBc/Hz FoM at 1 MHz offset. The second and third design were operating at 14-GHz with a power consumption range of 13-18.4mW and 14.6-20.5mW, respectively. The one with filtering technique achieved FoM of 184.8 dBc/Hz at 1 MHz whereas the one without inudctor filtering obtained FoM of 180.8 dBc/Hz at 1 MHz offset based on simulation

Power Reduction Techniques in Clock Distribution Networks with Emphasis on LC Resonant Clocking

In this thesis we propose a set of independent techniques in the overall concept of LC resonant clocking where each technique reduces power consumption and improve system performance. Low-power design is becoming a crucial design objective due to the growing demand on portable applications and the increasing difficulties in cooling and heat removal. The clock distribution network delivers the clock signal which acts as a reference to all sequential elements in the synchronous system. The clock distribution network consumes a considerable amount of power in synchronous digital systems. Resonant clocking is an emerging promising technique to reduce the power of the clock network. The inductor used in resonant clocking enables the conversion of the electric energy stored on the clock capacitance to magnetic energy in the inductor and vice versa. In this thesis, the concept of the slack in the clock skew has been extended for an LC fully-resonant clock distribution network. This extra slack in comparison to standard clock distribution networks can be used to reduce routing complexity, achieve reduction in wire elongation, total wire length, and power consumption. Simulation results illustrate that by utilizing the proposed approach, an average reduction of 53% in the number of wire elongations and 11% reduction in total wire length can be achieved. A dual-edge clocking scheme introduced in the literature to enable the operation of the flip-flop at the rising- and falling edges of the clock has been modified. The interval by which the charging elements in the flip-flop are being switched-on was reduced causing a reduction in power consumption. Simulating the flip-flop in STMicroelectronics 90-nm technology shows correct functionality of the Sense Amplifier flip-flop with a resonant clock signal of 500 MHz and a throughput of 1 GHz under process, voltage, and temperature (PVT) variations. Modeling the resonant system with the proposed flip-flop illustrates that dual-edge compared to single-edge triggering can achieve up to 58% reduction in power consumption when the clock capacitance is the dominating factor. The application of low-swing clocking to LC resonant clock distribution network has been investigated on-chip. The proposed low-swing resonant clocking scheme operates with one voltage supply and does not require an additional supply voltage. The Differential Conditional Capturing flip-flop introduced in the literature was modified to operate with a low-swing sinusoidal clock. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead. Modeling the clock network with the proposed flip-flop illustrates that low-swing clocking can achieve up to 58% reduction in the power consumption of the resonant clock. An analytical approach was introduced to estimate the required driver strength in the clock generator. Using the proposed approach early in the design stage reduces area and power overhead by eliminating the need for programmable switches in the driving circuit

Nonlinear Circuits For Signal Generation And Processing In Cmos

As Moore's law predicted, transistor scaling has continued unabated for more than half a century, resulting in significant improvement in speed, efficiency, and integration level. This has led to rapid growth of diverse computing and communications technologies, including the Internet and mobile telephony. Nevertheless, we still face the fundamental limit of noise from transistors and passive components. This noise limit becomes more critical at higher frequencies due to the decrease in intrinsic transistor gain as well as with voltage scaling that accompanies the transistor scaling. On the other hand, insufficient transistor gain and breakdown in silicon limits high-power signal generation at sub-millimeter frequencies that is essential in many security and medical applications, including detection of concealed weapons and bio/molecular spectroscopy for drug detection and breath analysis for disease diagnosis. To go beyond these limits, we propose a new circuit design methodology inspired by nonlinear wave propagation. This method is closely related to intriguing phenomena in other disciplines of physics such as nonlinear optics, fluid mechanics, and plasma physics. Based on this, in the first part of this study, we propose a passive 20-GHz frequency divider for the first time implemented in CMOS. This device has close to ideal noise performance with no DC power consumption, which can potentially reduce overall system power and phase noise in high-frequency synthesizers. Next, to achieve sensitivity toward the thermal noise limit, we propose a 10-GHz CMOS noise-squeezing amplifier. This amplifier enhances sensitivity of an input signal in one quadrature phase by 2.5 dB at the expense of degrading the other quadrature component. Lastly, we introduce an LC lattice to generate 2.7 V p[-] p , 6 ps pulses in CMOS using constructive nonlinear wave interaction. The proposed lattice exhibits the sharpest pulse width achieved for high-amplitude pulses (>1 V) in any CMOS processes

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation