554 research outputs found
Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas
This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next
generation 5G wireless network structure will be heterogeneous, the device
density and their mobility will increase and massive MIMO connectivity
capability will be widespread, the main investigated problem is formulated –
increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks.
The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes.
The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the
introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included.
The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation.
The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions.
The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and
measurement results for all designed radio frequency power amplifiers.
General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation.
5 papers, focusing on the subject of the discussed dissertation, have been
published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made
9 presentations at 9 scientific conferences at a national and international level.Dissertatio
RF transceiver design for electronic toll collection system (ETC) using compact dipole antenna
Electronic Toll Collection (ETC) system is one of the types of traffic control system that has rapid development in the recent years. ETC system is one of the major applications of Dedicated Short Range Communication (DSRC) which operates in the frequency band of 5.8GHz, used for the transfer of information between the road side unit (RSU) and the on board unit (OBU) which are situated at the toll station and on the vehicle respectively. The working of the system is based on RFID technology. ETC system is implemented in the 0.18microm CMOS technology, which is an aggressive technology in terms of its low cost and easy integration of the RF circuits.;A compact dipole antenna based low-cost RF transceiver for ETC system is designed in this thesis. Amplitude Shift Keying (ASK) modulation technique is employed in the implemented RF transceiver. In transmitter side, a class-E power amplifier is used to amplify the signal power. In order to send and receive the signal, a dipole antenna operating at a frequency of 5.8GHz is used. A low-power and energy efficient Low-Noise Amplifier (LNA) is used in the receiver block which consumes very less power and has a minimal noise figure compared with prior arts. A self-mixer is used for the down-conversion of the signal. Results of this design demonstrate the working of the transceiver at 5.8GHz frequency up to an input data rate of 400 Mbps
Interface Circuits for Microsensor Integrated Systems
ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.
Delta-Sigma Modulator based Compact Sensor Signal Acquisition Front-end System
The proposed delta-sigma modulator (M) based signal acquisition
architecture uses a differential difference amplifier (DDA) customized for dual
purpose roles, namely as instrumentation amplifier and as integrator of
M. The DDA also provides balanced high input impedance for signal
from sensors. Further, programmable input amplification is obtained by
adjustment of M feedback voltage. Implementation of other
functionalities, such as filtering and digitization have also been
incorporated. At circuit level, a difference of transconductance of DDA input
pairs has been proposed to reduce the effect of input resistor thermal noise of
front-end R-C integrator of the M. Besides, chopping has been
used for minimizing effect of Flicker noise. The resulting architecture is an
aggregation of functions of entire signal acquisition system within the single
block of M, and is useful for a multitude of dc-to-medium
frequency sensing and similar applications that require high precision at
reduced size and power. An implementation of this in 0.18-m CMOS process
has been presented, yielding a simulated peak signal-to-noise ratio of 80 dB
and dynamic range of 109dBFS in an input signal band of 1 kHz while consuming
100 W of power; with the measured signal-to-noise ratio being lower by
about 9 dB.Comment: 13 pages, 16 figure
A self-powered single-chip wireless sensor platform
Internet of things” require a large array of low-cost sensor nodes, wireless connectivity, low power operation and system intelligence. On the other hand, wireless biomedical implants demand additional specifications including small form factor, a choice of wireless operating frequencies within the window for minimum tissue loss and bio-compatibility This thesis describes a low power and low-cost internet of things system suitable for implant applications that is implemented in its entirety on a single standard CMOS chip with an area smaller than 0.5 mm2. The chip includes integrated sensors, ultra-low-power transceivers, and additional interface and digital control electronics while it does not require a battery or complex packaging schemes. It is powered through electromagnetic (EM) radiation using its on-chip miniature antenna that also assists with transmit and receive functions. The chip can operate at a short distance (a few centimeters) from an EM source that also serves as its wireless link. Design methodology, system simulation and optimization and early measurement results are presented
Design of a Low Voltage Class AB Variable Gain Amplifier (VGA)
A variable gain amplifier (VGA) is one of the most significant component in many applications such as analog to digital converter (ADC). In communication receiver, VGA is typically employed in a feedback loop to realize an automatic gain control (AGC), to provide constant signal power to baseband analog-to-digital converter (ADC) for unpredictable received signal strengths. Gain range, power consumption and bandwidth of ADC are strongly influenced by the performance of operational amplifier. VGA is the key element for amplifying process in ADC. However, current class AB VGA is experiencing the limit of bandwidth, which is not suitable for high speed automatic gain control AGC. In order to overcome these limitations a high linearity and wide bandwidth of VGA is indispensable. The aim of this research is to get higher gain and larger bandwidth for VGA. In this research, a low cost, low power voltage and wide bandwidth class AB VGA is designed to mitigate this constraint. Superiority of the proposed VGA has been confirmed by circuit simulation using CEDEC 0.18-μm CMOS process with the help of tools from Mentor Graphics in designing a 100-MHz VGA under 1V supply voltage draining total static power consumption less than 125uW. The results show that the circuit is able to work with high linearity and wide bandwidth by varying Rf and Rs. Therefore, the frequency response (Gain) and the wide bandwidth of this class AB VGA is better than previously reported class AB VGA. Consequently, this modified class AB VGA is appropriate for high speed applications
A Two Channel Analog Front end Design AFE Design with Continuous Time Σ-Δ Modulator for ECG Signal
In this context, the AFE with 2-channels is described, which has high impedance for low power application of bio-medical electrical activity. The challenge in obtaining accurate recordings of biomedical signals such as EEG/ECG to study the human body in research work. This paper is to propose Multi-Vt in AFE circuit design cascaded with CT modulator. The new architecture is anticipated with two dissimilar input signals filtered from 2-channel to one modulator. In this methodology, the amplifier is low powered multi-VT Analog Front-End which consumes less power by applying dual threshold voltage. Type -I category 2 channel signals of the first mode: 50 and 150 Hz amplified from AFE are given to 2nd CT sigma-delta ADC. Depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in a 0.18 um standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in 0.18 m standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, programmable gains from 52.6 dB to 72 dB, input referred noise of 3.5 μV in the amplifier bandwidth, NEF of 3
A 3rd-order Continuous-Time Low-Pass Sigma-Delta Analog-to-Digital Converter for Wideband Applications
This thesis presents the design of a 20 MHz bandwidth 3rd-order continuous-time low-pass sigma-delta analog-to-digital converter with low-noise and low-power consumption using TSMC 0.18 μm CMOS technology. The bandwidth of the system is selected to be able to accommodate WiMAX and other wireless network standards. A 3rd-order filter with feed-forward architecture is selected to achieve low-power consumption as well as less complexity. The system uses 3-bit flash quantizer to provide fast data conversion. The current-steering DAC not only achieves low-power and less current sensitivity, but also it helps directly inject the feedback signal without additional circuitries. In order to avoid degradation of the overall performance, cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9 dB in 20 MHz bandwidth, and consumes 31.735 mW from a 1.8 V supply. The entire circuit is driven by a sampling rate at 500 MHz. The measured in-band IM3 of this thesis is -69 dB with 600 mVp-p two tone signal peak-to-peak voltage
- …