RF transceiver design for electronic toll collection system (ETC) using compact dipole antenna

Electronic Toll Collection (ETC) system is one of the types of traffic control system that has rapid development in the recent years. ETC system is one of the major applications of Dedicated Short Range Communication (DSRC) which operates in the frequency band of 5.8GHz, used for the transfer of information between the road side unit (RSU) and the on board unit (OBU) which are situated at the toll station and on the vehicle respectively. The working of the system is based on RFID technology. ETC system is implemented in the 0.18microm CMOS technology, which is an aggressive technology in terms of its low cost and easy integration of the RF circuits.;A compact dipole antenna based low-cost RF transceiver for ETC system is designed in this thesis. Amplitude Shift Keying (ASK) modulation technique is employed in the implemented RF transceiver. In transmitter side, a class-E power amplifier is used to amplify the signal power. In order to send and receive the signal, a dipole antenna operating at a frequency of 5.8GHz is used. A low-power and energy efficient Low-Noise Amplifier (LNA) is used in the receiver block which consumes very less power and has a minimal noise figure compared with prior arts. A self-mixer is used for the down-conversion of the signal. Results of this design demonstrate the working of the transceiver at 5.8GHz frequency up to an input data rate of 400 Mbps

DESIGN OF A FOUR STAGES VCO USING A NOVEL DELAY CIRCUIT FOR OPERATION IN DISTRIBUTED BAND FREQUENCIES

The manuscript proposes a novel architecture of a delay cell that is implemented in 4-stage VCO which has the ability to operate in two distributed frequency bands. The operating frequency is chosen based on the principle of carrier mobility and the transistor resistance. The VCO uses dual delay input techniques to improve the frequency of operation. The design is implemented in Cadence 90nm GPDK CMOS technology and simulated results show that it is capable of operating in dual frequency bands of 55 MHz to 606 MHz and 857 MHz to 1049 MHz. At normal temperature (270) power consumption of the circuit is found to be 151μW at 606 MHz and 157μW at 1049 MHz respectively and consumes an area of 171.42µm2. The design shows good tradeoff between the parameters-operating frequency, phase noise and power consumption

Active Inductor with Feedback Resistor Based Voltage Controlled Oscillator Design for Wireless Applications

This paper presents active inductor based VCO design for wireless applications based on analysis of active inductor models (Weng-Kuo Cascode active inductor & Liang Regular Cascode active inductor) with feedback resistor technique. Embedment of feedback resistor results in the increment of inductance as well as the quality factor whereas the values are [email protected] (Liang) and [email protected] (Weng- Kuo). The Weng-Kuo active inductor based VCO shows a tuning frequency of 1.765GHz ~2.430GHz (31.7%), while consuming a power of 2.60 mW and phase noise of -84.15 dBc/Hz@1MHz offset. On the other hand, Liang active inductor based VCO shows a frequency range of 1.897GHz ~2.522GHz (28.28%), while consuming a power of 1.40 mW and phase noise of -80.79 dBc/Hz@1MHz offset. Comparing Figure-of-Merit (FoM), power consumption, output power and stability in performance, designed active inductor based VCOs outperform with the state-of-the-art

Phase Noise in CMOS Phase-Locked Loop Circuits

Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are investigated in different types of PLL designs. Hot carrier and negative bias temperature instability effects are analyzed from simulations and experiments. Phase noise of a CMOS phase-locked loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant model with additive noise sources in frequency domain is presented to analyze the phase noise. The modeled phase noise results are compared with the corresponding experimentally measured results on phase-locked loop chips fabricated in 0.5 m n-well CMOS process. With the scaling of CMOS technology and the increase of electrical field, MOS transistors have become very sensitive to hot carrier effect (HCE) and negative bias temperature instability (NBTI). These two reliability issues pose challenges to designers for designing of chips in deep submicron CMOS technologies. A new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm CMOS process to analyze the effects under HCE and NBTI. A 3V 1.2 GHz programmable phase-locked loop frequency synthesizer is designed in 0.5 μm CMOS technology. The frequency synthesizer is implemented using LC voltage-controlled oscillator (VCO) and a low power dual-modulus prescaler. The LC VCO working range is from 900MHz to 1.4GHz. Current mode logic (CML) is used in designing high speed D flip-flop in the dual-modulus prescaler circuits for low power consumption. The power consumption of the PLL chip is under 30mW. Fully differential LC VCO is used to provide high oscillation frequency. A new design of LC VCO using carbon nanotube (CNT) wire inductor has been proposed. The PLL design using CNT-LC VCO shows significant improvement in phase noise due to high-Q LC circuit

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

On the Investigation of a Novel Dual-Control-Gate Floating Gate Transistor for VCO Applications

A new MOS device called Dual-Control Gate Floating Gate Transistor (DCG-FGT) is used as a building block in analog design. This device offers new approaches in circuit design and allows developing new functionalities through two operating modes: Threshold Voltage Adjustable Mode, where the DCG-FGT behaves like a MOS transistor with an electrically adjustable threshold voltage. Mixer Signal Mode where the DCG-FGT can mix two independent signals on its floating gate. This device is developed to be fully compliant with CMOS Non Volatile Memory (NVM) process. An electrical model of the DCG-FGT has been implemented in an electrical simulator to be available for analog design. A DCG-FGT based ring oscillator is studied in this paper

A 2.4-GHz wireless sensor network for smart electronic shirts integration

A typical sensing module is composed of sensors, interface electronics, a radio-frequency (RF) CMOS transceiver and an associated antenna. A 2.4-GHz RF transceiver chip was fabricated in a UMC 0.18 μm CMOS process. The receiver has a sensibility of -60 dBm and consumes 6.3 mW from a 1.8 V supply. The transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. Innovative topics concerning efficient power management was taken into account during the design of the transceiver. A solution of individual sensing modules allows a plug-and-play solution. The target application is the integration of a wireless sensor network in smart electronic shirts, for monitoring the cardio-respiratory function and posture

Design of injection locked frequency divider in 65nm CMOS technology for mmW applications

In this paper, an Injection Locking Frequency Divider (ILFD) in 65 nm RF CMOS Technology for applications in millimeter-wave (mm-W) band is presented. The proposed circuit achieves 12.69% of locking range without any tuning mechanism and it can cover the entire mm-W band in presence of Process, Voltage and Temperature (PVT) variations by changing the Injection Locking Oscillator (ILO) voltage control. A design methodology flow is proposed for ILFD design and an overview regarding CMOS capabilities and opportunities for mm-W transceiver implementation is also exposed.Postprint (published version

A CCO-based Sigma-Delta ADC

Analog-to-digital converter (ADC) is one of the most important blocks in nowadays systems. Most of the data processing is done in the digital domain however, the physical world is analog. ADCs make the bridge between analog and digital domain. The constant and unstoppable evolution of the technology makes the dimensions of the transistors smaller and smaller, and the classical solutions of Sigma-Delta converters (ΣΔ) are becoming more challenging to design because they normally require high active gain blocks difficult to achieve in modern technologies. In recent years, the use of voltage-controlled oscillators (VCO) in ΣΔ converters has been widely explored, since they are used as quantizers and their implementations are mostly made with digital blocks, which is preferable with new technologies. In this work a second-order ΣΔ modulator based on two current-controlled oscillators (CCO) with a single output phase and an independent phase generator for each CCO that generates any desired number of phases using the oscillation of its CCO as reference has been proposed. This ΣΔ modulator was studied through a MATLAB/Simulink® model, obtaining promising results with the SNDR in the order of 75 dB, at a sampling frequency of 1 GHz, and a bandwidth of 5 MHz, corresponding to an ENOB of, approximately, 12 bits