10,190 research outputs found
Harnessing optical micro-combs for microwave photonics
In the past decade, optical frequency combs generated by high-Q
micro-resonators, or micro-combs, which feature compact device footprints, high
energy efficiency, and high-repetition-rates in broad optical bandwidths, have
led to a revolution in a wide range of fields including metrology, mode-locked
lasers, telecommunications, RF photonics, spectroscopy, sensing, and quantum
optics. Among these, an application that has attracted great interest is the
use of micro-combs for RF photonics, where they offer enhanced functionalities
as well as reduced size and power consumption over other approaches. This
article reviews the recent advances in this emerging field. We provide an
overview of the main achievements that have been obtained to date, and
highlight the strong potential of micro-combs for RF photonics applications. We
also discuss some of the open challenges and limitations that need to be met
for practical applications.Comment: 32 Pages, 13 Figures, 172 Reference
Fully Integrated Frequency and Phase Generation for a 6-18GHz Tunable Multi-Band Phased-Array Receiver in CMOS
Fully integrated frequency-phase generators
for a 6-18GHz wide-band phased-array receiver element are
presented that generate 5-7GHz and 9-12GHz first LO
signals with less than -95dBc/Hz phase noise at 100kHz
offset. Second LO signals with digitally controllable fourquadrant phase- and amplitude spread with better than 3°
resolution are generated and allow removal of systematic
reference clock skew as well as accurate selection of the
received signal phase. This frequency- and phase generation
scheme was successfully demonstrated in a 6-18GHz receiver
system configured as an electrical 4-element array
A wideband linear tunable CDTA and its application in field programmable analogue array
This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio
Low jitter phase-locked loop clock synthesis with wide locking range
The fast growing demand of wireless and high speed data communications has driven efforts to increase the levels of integration in many communications applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase noise for communications systems which employ a phase-locked loop for frequency and clock synthesis with on-chip VCO. This dictates an integrated CMOS implementation of the VCO with very low phase noise performance. The ring oscillator VCOs based on differential delay cell chains have been used successfully in communications applications, but thermal noise induced phase noise have to be minimized in order not to limit their applicability to some applications which impose stringent timing jitter and phase noise requirements on the PLL clock synthesizer. Obtaining lower timing jitter and phase noise at the PLL output also requires the minimization of noise in critical circuit design blocks as well as the optimization of the loop bandwidth of the PLL.
In this dissertation the fundamental performance limits of CMOS PLL clock synthesizers based on ring oscillator VCOs are investigated. The effect of flicker and thermal noise in MOS transistors on timing jitter and phase noise are explored, with particular emphasis on source coupled NMOS differential delay cells with symmetric load elements. Several new circuit architectures are employed for the charge pump circuit and phase-frequency detector (PFD) to minimize the timing jitter due to the finite dead zone in the PFD and the current mismatch in the charge pump circuit. The selection of the optimum PLL loop bandwidth is critical in determining the phase noise performance at the PLL output. The optimum loop bandwidth and the phase noise performance of the PLL is determined using behavioral simulations. These results are compared with transistor level simulated results and experimental results for the PLL clock synthesizer fabricated in a 0.35 µm CMOS technology with good agreement.
To demonstrate the proposed concept, a fully integrated CMOS PLL clock synthesizer utilizing integer-N frequency multiplier technique to synthesize several clock signals in the range of 20-400 MHz with low phase noise was designed. Implemented in a standard 0.35-µm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps (rms) and 38-ps (peak-to-peak) at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz.
The specific research contributions of this work include (1) proposing, designing, and implementing a new charge pump circuit architecture that matches current levels and therefore minimizes one source of phase noise due to fluctuations in the control voltage of the VCO, (2) an improved phase-frequency detector architecture which has improved characteristics in lock condition, (3) an improved ring oscillator VCO with excellent thermal noise induced phase noise characteristics, (4) the application of selfbiased techniques together with fixed bias to CMOS low phase noise PLL clock synthesizer for digital video communications ,and (5) an analytical model that describes the phase noise performance of the proposed VCO and PLL clock synthesizer
MUSTANG: 90 GHz Science with the Green Bank Telescope
MUSTANG is a 90 GHz bolometer camera built for use as a facility instrument
on the 100 m Robert C. Byrd Green Bank radio telescope (GBT). MUSTANG has an 8
by 8 focal plane array of transition edge sensor bolometers read out using
time-domain multiplexed SQUID electronics. As a continuum instrument on a large
single dish MUSTANG has a combination of high resolution (8") and good
sensitivity to extended emission which make it very competitive for a wide
range of galactic and extragalactic science. Commissioning finished in January
2008 and some of the first science data have been collected.Comment: 9 Pages, 5 figures, Presented at the SPIE conference on astronomical
instrumentation in 200
Low-error and broadband microwave frequency measurement in a silicon chip
Instantaneous frequency measurement (IFM) of microwave signals is a
fundamental functionality for applications ranging from electronic warfare to
biomedical technology. Photonic techniques, and nonlinear optical interactions
in particular, have the potential to broaden the frequency measurement range
beyond the limits of electronic IFM systems. The key lies in efficiently
harnessing optical mixing in an integrated nonlinear platform, with low losses.
In this work, we exploit the low loss of a 35 cm long, thick silicon waveguide,
to efficiently harness Kerr nonlinearity, and demonstrate the first on-chip
four-wave mixing (FWM) based IFM system. We achieve a large 40 GHz measurement
bandwidth and record-low measurement error. Finally, we discuss the future
prospect of integrating the whole IFM system on a silicon chip to enable the
first reconfigurable, broadband IFM receiver with low-latency.Comment: 13 pages, 7 figure
CMOS systems and circuits for sub-degree per hour MEMS gyroscopes
The objective of our research is to develop system architectures and CMOS circuits that interface with high-Q silicon microgyroscopes to implement navigation-grade angular rate sensors. The MEMS sensor used in this work is an in-plane bulk-micromachined mode-matched tuning fork gyroscope (M² – TFG
), fabricated on silicon-on-insulator substrate. The use of CMOS transimpedance amplifiers (TIA) as front-ends in high-Q MEMS resonant sensors is explored. A T-network TIA is proposed as the front-end for resonant capacitive detection. The T-TIA provides on-chip transimpedance gains of 25MΩ, has a measured capacitive resolution of 0.02aF /√Hz at 15kHz, a dynamic range of 104dB in a bandwidth of 10Hz and consumes 400μW of power. A second contribution is the development of an automated scheme to adaptively bias the mechanical structure, such that the sensor is operated in the mode-matched condition. Mode-matching leverages the inherently high quality factors of the microgyroscope, resulting in significant improvement in the Brownian noise floor, electronic noise, sensitivity and bias drift of the microsensor. We developed a novel architecture that utilizes the often ignored residual quadrature error in a gyroscope to achieve and maintain perfect mode-matching (i.e.0Hz split between the drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS implementation is developed that allows mode-matching of the drive and sense frequencies of a gyroscope at a fraction of the time taken by current state of-the-art techniques. Further, this mode-matching technique allows for maintaining a controlled separation between the drive and sense resonant frequencies, providing a means of increasing sensor bandwidth and dynamic range. The mode-matching CMOS IC, implemented in a 0.5μm 2P3M process, and control algorithm have been interfaced with a 60μm thick M2−TFG to implement an angular rate sensor with bias drift as low as 0.1°/hr ℃ the lowest recorded to date for a silicon MEMS gyro.Ph.D.Committee Chair: Farrokh Ayazi; Committee Member: Jennifer Michaels; Committee Member: Levent Degertekin; Committee Member: Paul Hasler; Committee Member: W. Marshall Leac
High Speed Chaos in Optical Feedback System with Flexible Timescales
We describe a new opto-electronic device with time-delayed feedback that uses
a Mach-Zehnder interferometer as passive nonlinearity and a semiconductor laser
as a current-to-optical-frequency converter. Bandlimited feedback allows tuning
of the characteristic time scales of both the periodic and high dimensional
chaotic oscillations that can be generated with the device. Our implementation
of the device produces oscillations in the frequency range of tens to hundreds
of MHz. We develop a model and use it to explore the experimentally observed
Andronov-Hopf bifurcation of the steady state and to estimate the dimension of
the chaotic attractor.Comment: 7 pages, 6 figures, to be published in IEEE J. Quantum Electro
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