37 research outputs found
A low-power native NMOS-based bandgap reference operating from â55°C to 125°C with Li-Ion battery compatibility
Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from â55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420ânA at 27°C
Power Management and SRAM for Energy-Autonomous and Low-Power Systems
We demonstrate the two first-known, complete, self-powered millimeter-scale computer systems.
These microsystems achieve zero-net-energy operation using solar energy harvesting and
ultra-low-power circuits. A medical implant for monitoring intraocular pressure (IOP) is presented
as part of a treatment for glaucoma. The 1.5mm3 IOP monitor is easily implantable because of its
small size and measures IOP with 0.5mmHg accuracy. It wirelessly transmits data to an external
wand while consuming 4.7nJ/bit. This provides rapid feedback about treatment efficacies to decrease
physician response time and potentially prevent unnecessary vision loss. A nearly-perpetual
temperature sensor is presented that processes data using a 2.1ΌW near-threshold ARM°R Cortex-
M3TM ÎŒP that provides a widely-used and trusted programming platform.
Energy harvesting and power management techniques for these two microsystems enable energy-autonomous
operation. The IOP monitor harvests 80nW of solar power while consuming only
5.3nW, extending lifetime indefinitely. This allows the device to provide medical information for
extended periods of time, giving doctors time to converge upon the best glaucoma treatment. The
temperature sensor uses on-demand power delivery to improve low-load dc-dc voltage conversion
efficiency by 4.75x. It also performs linear regulation to deliver power with low noise, improved
load regulation, and tight line regulation.
Low-power high-throughput SRAM techniques help millimeter-scale microsystems meet stringent
power budgets. VDD scaling in memory decreases energy per access, but also decreases stability
margins. These margins can be improved using sizing, VTH selection, and assist circuits,
as well as new bitcell designs. Adaptive Crosshairs modulation of SRAM power supplies fixes
70% of parametric failures. Half-differential SRAM design improves stability, reducing VMIN by
72mV.
The circuit techniques for energy autonomy presented in this dissertation enable millimeter-scale
microsystems for medical implants, such as blood pressure and glucose sensors, as well as
non-medical applications, such as supply chain and infrastructure monitoring. These pervasive
sensors represent the continuation of Bellâs Law, which accurately traces the evolution of computers
as they become smaller, more numerous, and more powerful. The development of
millimeter-scale massively-deployed ubiquitous computers ensures the continued expansion and
profitability of the semiconductor industry. NanoWatt circuit techniques will allow us to meet this
next frontier in IC design.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86387/1/grgkchen_1.pd
Integrated Circuits for Programming Flash Memories in Portable Applications
Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration
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Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design
The advances of the complementary metal-oxide-semiconductor (CMOS) technology manufacturing and design over the years have enabled a diverse range of applications across the power consumption, performance, and area (PPA) spectra. Many of the recent and prospective applications rely on the availability of energy-autonomous, miniaturized systems, i.e., ultra-low power (ULP) VLSI systems, which are generally characterized by extreme resource limitations. Some examples of applications are wireless sensing platforms, body-area sensor networks (BASN), biomedical and implantable devices, wearables, hearables, and monitors. Within the context of such applications, the key requirements are long lifetime and miniaturized size (sub-/millimeter-scale). In order to enable both requirements, energy-efficiency is the key metric. It allows for extended battery lifetime and operation with the energy that can be harvested from the environment, and it limits the size (volume) of the energy sources utilized to power these systems.
Ultra-low voltage (ULV) operation is a key technique in which the VDD of circuits is reduced from nominal to near or below the threshold voltage of the transistor. It is a powerful knob that has been largely exploited by designers in order to achieve ultra-low power consumption and high energy-efficiency in CMOS. Existing ULP VLSI systems typically operate at a lower supply voltage thereby reducing their energy consumption by one to two orders of magnitude in order to enable the aforementioned applications.
While supply voltage scaling is a promising measure for achieving low power and reducing energy consumption, it brings up several challenges. One critical issue is the leakage energy dissipated by the devices, which is magnified in portion to the total energy consumption at ULV. The reason is that, as VDD scales from nominal to near-threshold and sub-threshold, transistors become increasingly slower and they accumulate more leakage (i.e., static) power over longer cycle times. This energy waste accounts for a significant portion of the system's total energy consumption, offsets the gains provided by voltage scaling, defines the minimum energy per operation, and poses a practical limit for the system's energy-efficiency.
This thesis presents selected research works on ultra-low leakage, energy-efficient digital integrated circuit design. More specifically, it describes novel and key techniques for minimizing the energy waste of idle/underutilized and always-on hardware. The main goal of such techniques is to push the envelope of energy-efficiency in energy-autonomous, miniaturized VLSI systems. Such techniques are applied to key building blocks of emerging mobile and embedded computing devices resulting in state-of-the-art energy-efficiencies
Projeto de referĂȘncia de tensĂŁo subbandgap
A referĂȘncia de tensĂŁo Ă© um circuito muito relevante por fornecer sua tensĂŁo de saĂda para diversos circuitos analĂłgicos, sinais mistos e digitais, alĂ©m de ter sido um importante tĂłpico de estudo em circuitos integrados por mais de 50 anos. Uma referĂȘncia de tensĂŁo deve providenciar uma tensĂŁo estĂĄvel com baixa sensibilidade Ă variaçÔes na temperatura, tensĂŁo de alimentação, caracterĂsticas de processo de fabricação e estresses no encapsulamento, alĂ©m de outros parĂąmetros especĂficos de cada aplicação. Esse tipo de circuito funciona com o cancelamento da dependĂȘncia tĂ©rmica entre duas grandezas elĂ©tricas, normalmente implementados pela soma ponderada de dois efeitos fĂsicos independentes com dependĂȘncias tĂ©rmicas opostas. Circuitos denominados bandgap empregam a deriva tĂ©rmica negativa de uma junção semicondutora para gerar a grandeza elĂ©trica com dependĂȘncia complementar Ă temperatura absoluta, enquanto o potencial tĂ©rmico, advindo da constante de Boltzmann e da carga do elĂ©tron, normalmente Ă© utilizado para gerar a grandeza elĂ©trica com dependĂȘncia proporcional Ă temperatura absoluta. Considerando que essas grandezas tambĂ©m dependem do processo de fabricação, o desempenho de referĂȘncia Ă© muito impactado pela variabilidade de fabricação. Um projeto que apresente robustez Ă variabilidade Ă© mandatĂłrio para aumentar a precisĂŁo do circuito. Consequentemente, este trabalho apresenta o projeto de uma referĂȘncia de tensĂŁo subbandgap de baixa variabilidade comportamental. Foi implementada uma fonte de corrente ISQ para a polarização de todos os blocos do circuito com uma corrente que apresenta baixa variabilidade comportamental. Foram implementados Self-Cascode MOSFET (SCM) e Pares Diferenciais Desbalanceados para a geração de tensĂ”es proporcionais Ă temperatura absoluta. As topologias empregadas sĂŁo descritas analiticamente e o modelo ACM foi utilizado durante o projeto. O circuito Ă© formando somente por transistores no processo de fabricação de 180 nm CMOS da XFAB. As simulaçÔes realizadas em schematic view resultaram em uma tensĂŁo de referĂȘncia de 738 mV apresentando TC mĂ©dio de 37,6 ppm/ C, consumindo 8,809 ÎŒV em uma tensĂŁo de alimentação de 1,8 V. SimulaçÔes Monte Carlo foram conduzidas para avaliar o comportamento do circuito frente Ă variabilidade comportamental, apresentando resultados comparĂĄveis Ă artigos publicados em convençÔes internacionais.The voltage reference is a very relevant circuit for providing its output voltage to many analog, mixed-signal and digital circuits, and has been an important topic of study in integrated circuits for more than 50 years. A voltage reference must provide a stable voltage with low sensitivity to variations in temperature, supply voltage, manufacturing process characteristics and package stresses, as well as other application-specific parameters. This type of circuit works by canceling the thermal dependence between two electrical quantities, usually implemented by the weighted sum of two independent physical effects with opposite thermal dependencies. Circuits called bandgap employ the negative thermal drift of a semiconductor junction to generate the electric quantity with complementary temperature dependence, while the thermal potential, related from the Boltzmannâs constant and the electron charge, is normally used to generate the proportional term. Since these quantities are also dependent on the fabrication process, the reference performance is greatly impacted by fabrication variability. Reduction or a design that exhibits robustness to variability is mandatory to increase the circuit accuracy. Hence, this paper presents the design of a subbandgap voltage reference with low behavioral variability. An ISQ current source was implemented for biasing all the circuit blocks with a current that exhibits low behavioral variability. Self-Cascode MOSFET (SCM) and Unbalanced Differential Pairs were implemented for the generation proportional to absolute temperature terms. The topologies employed are described analytically and the ACM model was used during the design. The circuit is formed only by transistors in XFABâs 180 nM CMOS manufacturing process. Simulations performed in schematic view resulted in a reference voltage of 738 mV showing average TC of 37,6 ppm/ C, consuming 8,809 ÎŒV at a supply voltage of 1,8 V. Monte Carlo simulations were conducted to evaluate the circuit behavior against behavioral variability, presenting results comparable to papers published in international conventions
Low Voltage Low Power Analogue Circuits Design
DisertaÄnĂ prĂĄce je zamÄĆena na vĂœzkum nejbÄĆŸnÄjĆĄĂch metod, kterĂ© se vyuĆŸĂvajĂ pĆi nĂĄvrhu analogovĂœch obvodĆŻ s vyuĆŸitĂ nĂzkonapÄĆ„ovĂœch (LV) a nĂzkopĆĂkonovĂœch (LP) struktur. Tyto LV LP obvody mohou bĂœt vytvoĆeny dĂky vyspÄlĂœm technologiĂm nebo takĂ© vyuĆŸitĂm pokroÄilĂœch technik nĂĄvrhu. DisertaÄnĂ prĂĄce se zabĂœvĂĄ prĂĄvÄ pokroÄilĂœmi technikami nĂĄvrhu, pĆedevĆĄĂm pak nekonvenÄnĂmi. Mezi tyto techniky patĆĂ vyuĆŸitĂ prvkĆŻ s ĆĂzenĂœm substrĂĄtem (bulk-driven - BD), s plovoucĂm hradlem (floating-gate - FG), s kvazi plovoucĂm hradlem (quasi-floating-gate - QFG), s ĆĂzenĂœm substrĂĄtem s plovoucĂm hradlem (bulk-driven floating-gate - BD-FG) a s ĆĂzenĂœm substrĂĄtem s kvazi plovoucĂm hradlem (quasi-floating-gate - BD-QFG). PrĂĄce je takĂ© orientovĂĄna na moĆŸnĂ© zpĆŻsoby implementace znĂĄmĂœch a modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m nebo mix-mĂłdu. Mezi tyto prvky lze zaÄlenit zesilovaÄe typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za ĂșÄelem potvrzenĂ funkÄnosti a chovĂĄnĂ vĂœĆĄe zmĂnÄnĂœch struktur a prvkĆŻ byly vytvoĆeny pĆĂklady aplikacĂ, kterĂ© simulujĂ usmÄrĆovacĂ a induktanÄnĂ vlastnosti diody, dĂĄle pak filtry dolnĂ propusti, pĂĄsmovĂ© propusti a takĂ© univerzĂĄlnĂ filtry. VĆĄechny aktivnĂ prvky a pĆĂklady aplikacĂ byly ovÄĆeny pomocĂ PSpice simulacĂ s vyuĆŸitĂm parametrĆŻ technologie 0,18 m TSMC CMOS. Pro ilustraci pĆesnĂ©ho a ĂșÄinnĂ©ho chovĂĄnĂ struktur je v disertaÄnĂ prĂĄci zahrnuto velkĂ© mnoĆŸstvĂ simulaÄnĂch vĂœsledkĆŻ.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the nonâconventional ones which are bulkâdriven (BD), floatingâgate (FG), quasiâfloatingâgate (QFG), bulkâdriven floatingâgate (BDâFG) and bulkâdriven quasiâfloatingâgate (BDâQFG) techniques. The thesis also looks at ways of implementing structures of wellâknown and modern active elements operating in voltageâ, currentâ, and mixedâmode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fullyâdifferential second generation current conveyor (FBâCCII), fullyâbalanced differential difference amplifier (FBâDDA), voltage differencing transconductance amplifier (VDTA), currentâcontrolled current differencing buffered amplifier (CCâCDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diodeâless rectifier and inductance simulations, as well as lowâpass, bandâpass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.
Subthreshold design of ultra low-power analog modules
Il consumo di potenza rappresenta lâindicatore chiave delle performance di recenti applicazioni portatili, come dispositivi medici impiantabili o tag RFID passivi, allo scopo di aumentare, rispettivamente, i tempi di funzionamento o i range operativi. La riduzione della tensione di alimentazione si Ăš dimostrata lâapproccio migliore per ridurre il consumo di potenza dei sistemi digitali integrati. Al fine di tenere il passo con la riduzione delle tensioni di alimentazione, anche le sezioni analogiche dei sistemi mixed signal devono essere in grado di funzionare con livelli di tensione molto bassi. Di conseguenza, sono richieste nuove metodologie di progettazione analogica e configurazioni circuitali innovative in grado di lavorare con tensioni di alimentazioni bassissime, dissipando una potenza estremamente bassa. Il regime di funzionamento sottosoglia consente di ridurre notevolmente le tensioni applicabili ai dispositivi ed si contraddistingue per i livelli di corrente molto bassi, rispetto al ben noto funzionamento in forte inversione. Queste due caratteristiche sono state sfruttate nella realizzazione di moduli analogici di base ultra low voltage, low power.
Tre nuove architetture di riferimenti di tensione, che lavorano con tutti i transistor polarizzati in regime sottosoglia, sono stati fabbricati in tecnologia CMOS 0.18 ÎŒm. I tre circuiti si basano sullo stesso principio di funzionamento per compensare gli effetti della variazione della temperatura sulla tensione di riferimento generata. Tramite il principio di funzionamento proposto, la tensione di riferimento puĂČ essere approssimata con la differenza delle tensioni di soglia, a temperatura ambiente, dei transistor. Misure sperimentali sono state effettuate su set con piĂč di 30 campioni per ogni configurazione circuitale. Una dettagliata analisi statistica ha dimostrato un consumo medio di potenza che va da pochi nano watt a poche decine di nano watt, mentre la minima tensione di alimentazione, raggiunta da una delle tre configurazioni, Ăš di soli 0.45 V. Le tensioni di riferimento generate sono molto precise rispetto alle variazioni della temperatura e della tensione di alimentazione, infatti sono stati ottenuti coefficienti di temperatura e line sensitivity medi a partire rispettivamente da 165 ppm/°C e 0.065 %/V.
Inoltre, Ăš stata trattata anche la progettazione di amplificatori ultra low voltage, low power. Sono state illustrate linee guida dettagliate per la progettazione di amplificatori sottosoglia e le stesse sono state applicate per la realizzazione di un amplificatore a due stadi, con compensazione di Miller, funzionante con una tensione di alimentazione di 0.5 V. I risultati sperimentali dellâop amp proposto, fabbricato in tecnologia CMOS 0.18 ÎŒm, hanno mostrato un guadagno DC ad anello aperto di 70 dB, un prodotto banda guadagno di 18 kHz ed un consumo di potenza di soli 75 nW. I risultati delle misure sperimentali dimostrano che gli amplificatori operazionali in sottosoglia rappresentano una soluzione molto interessante nella realizzazione di applicazioni efficienti in termini energetici per gli attuali sistemi elettronici portatili. Dal confronto con amplificatori ultra low power, low voltage presenti in letteratura, si evince che la soluzione proposta offre un miglior compromesso tra velocitĂ , potenza dissipata e capacitĂ di carico
ReferĂȘncias de tensĂŁo integradas CMOS : testes, medidas e caracterização tĂ©rmica
Este trabalho descreve o setup de medidas e os resultados experimentais de uma ReferĂȘncia de TensĂŁo somente com transistores NMOS baseada no ponto ZTC. Os transistores Zero- VT sĂŁo usados como cargas ativas no circuito aberto e de feedback do circuito. Os resultados de medição de 10 amostras (processo 130 nm CMOS) do mesmo lote mostram que o circuito pode operar em 0,6 V de tensĂŁo mĂnima de alimentação, produz um Vref 0,372 V com 3 mV de desvio padrĂŁo, em comparação com 0,450 V e 29,2 mV respectivamente da simulação pĂłs-layout. AlĂ©m disso, o circuito ocupa uma ĂĄrea de apenas 0,006 mm 2. O coeficiente de temperatura medido de -55 oC a 75 oC Ă© 76 ppm / oC para alimentação nominal de 1,2 V. O consumo de energia Ă temperatura ambiente e a alimentação de 1,2 V Ă© de cerca de 0,9 ÎŒW. O circuito atinge um line sensitivity de apenas 0.177 % / V. O PSR foi medido em 500 Hz, 1 Khz, 10Khz e 100Khz e os resultados foram -27,5 dB, -23,5, -11,5 e -9,42 respectivamente.This work describes the measurement setup and results of NMOS-Only Voltage Reference based on the Zero Temperature Coefficient (ZTC) transistor point. Zero-VT transistors are used as active loads in the open and feedback loop of the circuit. Measurement results from 10 samples (130 nm CMOS process) of the same batch shows that circuit can operate at 0.6 minimum supply voltage, produces a Vref of 0.372 V with 3 mV of standard deviation, in comparison of 0.450 V and 29.2 mV respectively for post-layout simulation. Also the circuit occupy a 0.006 mm2 area. Measured temperature coefficient from -55 oC to 75 oC is 76 ppm/oC for nominal 1.2 V supply. Power consumption at room temperature and 1.2 V supply is around 0.9 ÎŒW. The circuit achieve a line sensitivity of only 0.177 %/V. The PSR was measured in 500 Hz, 1 Khz, 10Khz and 100Khz and the results was -27.5 dB, -23.5, -11.5 and -9.42 respectively
Low Power Circuits for Smart Flexible ECG Sensors
Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research.
A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording.
A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops.
A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W