General rational approximation of Gaussian wavelet series and continuous-time gm-C filter implementation

© 2020 John Wiley & Sons, Ltd. This is the accepted version of the following article: Li, M, Sun, Y. General rational approximation of Gaussian wavelet series and continuous‐time g m ‐C filter implementation. Int J Circ Theor Appl. 2020; 1– 17., which has been published in final form at https://doi.org/10.1002/cta.2834.A general method of rational approximation for Gaussian wavelet series and Gaussian wavelet filter circuit design with simple gm-C integrators is presented in this work. Firstly, the multi-order derivatives of Gaussian function are analysed and proved as wavelet base functions. Then a high accuracy general approximation model of Gaussian wavelet series is constructed and the transfer function of first order derivative of Gaussian wavelet filter is obtained using quantum differential evolution (QDE) algorithm. Thirdly, as an example, a 5th order continuous-time analogue first order derivative of Gaussian wavelet filter circuit is designed based on multiple loop feedback structure with simple gm-C integrator as the basic blocks. Finally, simulation results demonstrate the proposed method is an excellent way for the wavelet transform implementation. The designed first order derivative of Gaussian wavelet filter circuit operates from a 0.53V supply voltage and a bias current 2.5nA. The power dissipation of the wavelet filter circuit at the basic scale is 41.1nW. Moreover, the high accuracy QRS detection based on the designed wavelet filter has been validated in application analysis.Peer reviewe

Low-voltage embedded biomedical processor design

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 180-190).Advances in mobile electronics are fueling new possibilities in a variety of applications, one of which is ambulatory medical monitoring with body-worn or implanted sensors. Digital processors on such sensors serve to analyze signals in real-time and extract key features for transmission or storage. To support diverse and evolving applications, the processor should be flexible, and to extend sensor operating lifetime, the processor should be energy-efficient. This thesis focuses on architectures and circuits for low power biomedical signal processing. A general-purpose processor is extended with custom hardware accelerators to reduce the cycle count and energy for common tasks, including FIR and median filtering as well as computing FFTs and mathematical functions. Improvements to classic architectures are proposed to reduce power and improve versatility: an FFT accelerator demonstrates a new control scheme to reduce datapath switching activity, and a modified CORDIC engine features increased input range and decreased quantization error over conventional designs. At the system level, the addition of accelerators increases leakage power and bus loading; strategies to mitigate these costs are analyzed in this thesis. A key strategy for improving energy efficiency is to aggressively scale the power supply voltage according to application performance demands. However, increased sensitivity to variation at low voltages must be mitigated in logic and SRAM design. For logic circuits, a design flow and a hold time verification methodology addressing local variation are proposed and demonstrated in a 65nm microcontroller functioning at 0.3V. For SRAMs, a model for the weak-cell read current is presented for near-V supply voltages, and a self-timed scheme for reducing internal bus glitches is employed with low leakage overhead. The above techniques are demonstrated in a 0.5-1.OV biomedical signal processing platform in 0.13p-Lm CMOS. The use of accelerators for key signal processing enabled greater than 10x energy reduction in two complete EEG and EKG analysis applications, as compared to implementations on a conventional processor.by Joyce Y. S. Kwong.Ph.D

CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications

Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non- Linear (ELIN) systems. They can handle large-signals in a low power environment under half the capacitor area required by the more popular ELIN Log-domain filters. Their inherent class-AB nature stems from the odd property of the sinh function at the heart of their companding operation. Despite this early realisation, the Sinh filtering paradigm has not attracted the interest it deserves to date probably due to its mathematical and circuit-level complexity. This Thesis presents an overview of the CMOS weak inversion Sinh filtering paradigm and explains how biomedical systems of low- to audio-frequency range could benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of high order Sinh continuous–time filters and more importantly to confirm their micro-power consumption and 100+ dB of DR through measured results presented for the first time. Novel high order Sinh topologies are designed by means of a systematic mathematical framework introduced. They employ a recently proposed CMOS Sinh integrator comprising only p-type devices in its translinear loops. The performance of the high order topologies is evaluated both solely and in comparison with their Log domain counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a corresponding and also novel Log domain class-AB topology, confirming that Sinh filters constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense of higher complexity and power consumption. The theoretical findings are validated by means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a 0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of ~60dB and 74μW power consumption from 2V power supply

ENERGY-EFFICIENT FEATURE EXTRACTION ENGINE AND SECURE CHIP IDENTIFICATION FOR UBIQUITOUS SURVEILLANCE

Ph.DDOCTOR OF PHILOSOPH

Development of a sub-miniature acoustic sensor for wireless monitoring of heart rate

This thesis presents the development of a non-invasive, wireless, low-power, phonocardiographic (PCG) or heart sound sensor platform suitable for long-term monitoring of heart function. The core of this development process involves a study of the feasibility of this conceptual system and the development of a prototype mixed-signals integrated circuit (IC) to form the integral component of the proposed sensor. The feasibility study of the proposed long-term monitoring sensor is divided into two main parts. The first part of the study investigates the technological aspect of the conceptual system, via a system level design. This is to prove the technological or operational feasibility of the system, where the system can be built completely using discrete, off-the-shelf electronics components to satisfy the size, power consumption, battery life and operational requirements of the sensor platform. The second part of the study concentrates on the post-processing of the heart sounds and murmurs or PCG data recorded. This is where a number of different de-noising algorithms are studied and their relative performance compared when applied to a variety of different noisy heart sound signals that would likely be acquired using the proposed sensor in everyday life. This was done to demonstrate the functional feasibility of the proposed system, where the ambient acoustic noise in the recorded PCG data can be effectively suppressed and therefore meaningful analysis of heart function i.e. heart rate, can be performed on the data. After the feasibility of the conceptual system has been demonstrated, the final part of this thesis discusses the synthesis and testing of a 0.35 μm CMOS technology prototype mixed analog-digital integrated circuit (IC) to miniaturise part of this sensor platform outlined in the system level design, conducted in the earlier part of this thesis, to achieve the objective specifications – in terms of the size and power consumption. A new implementation of the multi-tanh triplet transconductor is introduced to construct a pair of 100 nW analogue 4th order Gm-C signal conditioning filters. Furthermore, a 7 μW digital circuit was designed to drive the analog-to-digital conversion cycle of the Linear Technology LTC1288 ADC and synchronise the ADC’s output to generate the Manchester encoded data compatible with the Holt Integrated Circuit HI-15530 Manchester Encoder/Decoder

Modeling and design of an active silicon cochlea

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references.Silicon cochleas are inspired by the biological cochlea and perform efficient spectrum analysis: They realize a bank of constant-Q Nth-order filters with O(N) efficiency rather than O(N²) efficiency due to their use of an exponentially tapered filter cascade. They are useful in speech-recognition front ends, cochlear implants, and hearing aids, especially as architectures for improving spectral analysis in noisy environments and for performing low-power spectrum analysis. In this thesis I describe four contributions towards improving the state-of-the-art in silicon-cochlea design, two of which involve theoretical modeling, and two of which involve integrated-circuit design. On the theoretical side, I first show that a simple rational approximation to distributed partition impedances in the biological cochlea captures its essential features and enables an efficient artificial implementation achieving maximum gain in a minimum number of stages while still maintaining stability. In particular, I show that the terminating impedance of the cochlea is crucial for its stability and discuss various analytic methods for termination. Second, I derive a novel composite artificial cochlear architecture composed of a cascade of all-pass second-order filters from a first-principles analysis of the biological cochlear transmission line. The novel all-pass architecture reduces phase lag and group delay in the silicon cochlea, a problem in prior designs, sharpens its high-frequency rolloff slopes, increases its frequency selectivity, and improves its nonlinear compression characteristics. On the circuit side, I first present a novel current-mode log-domain topology that simultaneously increases signal-to-noise ratio (SNR) and dynamic range while lowering power consumption in resonant filters with high quality factor Q.(cont.) The novel topology is validated in a second-order low-pass resonant filter, which is employed in the silicon cochlea, demonstrating a reduction in power consumption and increase in SNR by a factor of Q. When bias currents in the filter are adjusted as the signal level varies, this technique enables an improvement in maximum SNR by a factor of Q and an increase in maximum non-distorted signal power and dynamic range by a factor of Q⁴. Measurements from a chip in a 0.18-[mu]m 1.1-V CMOS technology achieve a quiescent power consumption of 580-nW at a 15-kHz center frequency with a maximum SNR of 41.3dB and dynamic range of 76dB for a Q=4. Finally, I describe a current-mode -stage 0.18-[mu]m silicon cochlea that achieves 79dB of dynamic range with 41-[mu]W power consumption on a 1-V power supply over a usable 3.5kHz-14kHz frequency range. These numbers represent an 18dB improvement in dynamic range and a 12.5x reduction in power consumption over prior state-of-the-art silicon cochleas.by Serhii M. Zhak.Ph.D

Robust Algorithms for Unattended Monitoring of Cardiovascular Health

Cardiovascular disease is the leading cause of death in the United States. Tracking daily changes in one’s cardiovascular health can be critical in diagnosing and managing cardiovascular disease, such as heart failure and hypertension. A toilet seat is the ideal device for monitoring parameters relating to a subject’s cardiac health in his or her home, because it is used consistently and requires no change in daily habit. The present work demonstrates the ability to accurately capture clinically relevant ECG metrics, pulse transit time based blood pressures, and other parameters across subjects and physiological states using a toilet seat-based cardiovascular monitoring system, enabled through advanced signal processing algorithms and techniques. The algorithms described herein have been designed for use with noisy physiologic signals measured at non-standard locations. A key component of these algorithms is the classification of signal quality, which allows automatic rejection of noisy segments before feature delineation and interval extractions. The present delineation algorithms have been designed to work on poor quality signals while maintaining the highest possible temporal resolution. When validated on standard databases, the custom QRS delineation algorithm has best-in-class sensitivity and precision, while the photoplethysmogram delineation algorithm has best-in-class temporal resolution. Human subject testing on normative and heart failure subjects is used to evaluate the efficacy of the proposed monitoring system and algorithms. Results show that the accuracy of the measured heart rate and blood pressure are well within the limits of AAMI standards. For the first time, a single device is capable of monitoring long-term trends in these parameters while facilitating daily measurements that are taken at rest, prior to the consumption of food and stimulants, and at consistent times each day. This system has the potential to revolutionize in-home cardiovascular monitoring