MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

MOSFET ZTC condition analysis for a self-biased current reference design

In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/o C from -40 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V

A 0.3-1.2V Schottky-Based CMOS ZTC Voltage Reference

A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3V up to 1.2V and outputs three different reference voltages using Standard-VT (SVT), Low-VT (LVT), and Zero-VT (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13-µm CMOS process show a worst-case normalized standard deviation (σ/µ) of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TCeff) range from 140 to 200 ppm/oC over the full commercial temperature range. At room temperature (25oC), line sensitivity in the ZVT VR is just 1.3%/100mV, over the whole supply range. The proposed reference draws around 5 µW and occupies 0.014 mm2 of silicon area

Low temperature sensitivity CMOS transconductor based on GZTC MOSFET condition

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/ºC

Zero temperature coefficient bias in MOS devices. Dependence on interface traps density, application to MOS dosimetry

In this paper the influence of temperature fluctuations on the response of thick gate oxide metal oxide semiconductor dosimeters is reviewed and the zero temperature coefficient (ZTC) method is evaluated for error compensation. The response of the ZTC current to irradiation is studied showing that the error compensation impoverishes with absorbed dose. Finally, an explanation and analytic expression for the shifts in the ZTC current with irradiation based on the interface traps creation is proposed and verified with experimental data.Fil: Carbonetto, Sebastián Horacio. Universidad de Buenos Aires. Facultad de Ingeniería; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: García Inza, Mariano Andrés. Universidad de Buenos Aires. Facultad de Ingeniería; ArgentinaFil: Lipovetzky, José. Universidad de Buenos Aires. Facultad de Ingeniería; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Redin, Eduardo Gabriel. Universidad de Buenos Aires. Facultad de Ingeniería; ArgentinaFil: Sambuco Salomone, Lucas Ignacio. Universidad de Buenos Aires. Facultad de Ingeniería; ArgentinaFil: Faigon, Adrian Nestor. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad de Buenos Aires. Facultad de Ingeniería; Argentin

A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches

High-temperature integrated circuit (IC) design is one of the new frontiers in microelectronics that can significantly improve the performance of the electrical systems in extreme environment applications, including automotive, aerospace, well-logging, geothermal, and nuclear. Power modules (DC-DC converters, inverters, etc.) are key components in these electrical systems. Power-to-volume and power-to-weight ratios of these modules can be significantly improved by employing silicon carbide (SiC) based power switches which are capable of operating at much higher temperature than silicon (Si) and gallium arsenide (GaAs) based conventional devices. For successful realization of such high-temperature power electronic circuits, associated control electronics also need to perform at high temperature. In any power converter, gate driver circuit performs as the interface between a low-power microcontroller and the semiconductor power switches. This dissertation presents design, implementation, and measurement results of a silicon-on-insulator (SOI) based high-temperature (\u3e200 _C) and high-voltage (\u3e30 V) universal gate driver integrated circuit with high drive current (\u3e3 A) for SiC power switches. This mixed signal IC has primarily been designed for automotive applications where the under-hood temperature can reach 200 _C. Prototype driver circuits have been designed and implemented in a Bipolar-CMOS- DMOS (BCD) on SOI process and have been successfully tested up to 200 _C ambient temperature driving SiC switches (MOSFET and JFET) without any heat sink and thermal management. This circuit can generate 30V peak-to-peak gate drive signal and can source and sink 3A peak drive current. Temperature compensating and temperature independent design techniques are employed to design the critical functional units like dead-time controller and level shifters in the driver circuit. Chip-level layout techniques are employed to enhance the reliability of the circuit at high temperature. High-temperature test boards have been developed to test the prototype ICs. An ultra low power on-chip temperature sensor circuit has also been designed and integrated into the gate-driver die to safeguard the driver circuit against excessive die temperature (_ 220 _C). This new temperature monitoring approach utilizes a reverse biased p-n junction diode as the temperature sensing element. Power consumption of this sensor circuit is less than 10 uW at 200 _C

Design of a low-voltage low-power CMOS current reference

Nowadays, the current reference circuits can be improved using the CMOS weak inversion characteristic, this thesis deals different current reference structures in order to design a circuit which figures of merit can be reduced like the temperature coefficient, power consumption, and load and process sensitivity...Hoy en día, los espejos de corriente o current reference, pueden ser mejorados con las características de inversión débil subthreshold-region cuando son construidos con tecnología CMOS, está tesis trata sobre cuatro estructuras de current reference basadas en un circuito de solo tres transistores, las figuras de merito como coeficiente de temperatura, consumo de potencia, y sensibilidad de carga y proceso son obtenidas en cada una de las estructuras, y posteriormente son comparadas para disernir cual de las implementaciones ha presentado un mejor desempeño..

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph