Capacity, Fidelity, and Noise Tolerance of Associative Spatial-Temporal Memories Based on Memristive Neuromorphic Network

We have calculated the key characteristics of associative (content-addressable) spatial-temporal memories based on neuromorphic networks with restricted connectivity - "CrossNets". Such networks may be naturally implemented in nanoelectronic hardware using hybrid CMOS/memristor circuits, which may feature extremely high energy efficiency, approaching that of biological cortical circuits, at much higher operation speed. Our numerical simulations, in some cases confirmed by analytical calculations, have shown that the characteristics depend substantially on the method of information recording into the memory. Of the four methods we have explored, two look especially promising - one based on the quadratic programming, and the other one being a specific discrete version of the gradient descent. The latter method provides a slightly lower memory capacity (at the same fidelity) then the former one, but it allows local recording, which may be more readily implemented in nanoelectronic hardware. Most importantly, at the synchronous retrieval, both methods provide a capacity higher than that of the well-known Ternary Content-Addressable Memories with the same number of nonvolatile memory cells (e.g., memristors), though the input noise immunity of the CrossNet memories is somewhat lower

Architecture of a cognitive non-line-of-sight backhaul for 5G outdoor urban small cells

Densely deployed small cell networks will address the growing demand for broadband mobile connectivity, by increasing access network capacity and coverage. However, most potential small cell base station (SCBS) locations do not have existing telecommunication infrastructure. Providing backhaul connectivity to core networks is therefore a challenge. Millimeter wave (mmW) technologies operated at 30-90GHz are currently being considered to provide low-cost, flexible, high-capacity and reliable backhaul solutions using existing roof-mounted backhaul aggregation sites. Using intelligent mmW radio devices and massive multiple-input multiple-output (MIMO), for enabling point-to-multipoint (PtMP) operation, is considered in this research. The core aim of this research is to develop an architecture of an intelligent non-line-sight (NLOS) small cell backhaul (SCB) system based on mmW and massive MIMO technologies, and supporting intelligent algorithms to facilitate reliable NLOS street-to-rooftop NLOS SCB connectivity. In the proposed architecture, diffraction points are used as signal anchor points between backhaul radio devices. In the new architecture the integration of these technologies is considered. This involves the design of efficient artificial intelligence algorithms to enable backhaul radio devices to autonomously select suitable NLOS propagation paths, find an optimal number of links that meet the backhaul performance requirements and determine an optimal number of diffractions points capable of covering predetermined SCB locations. Throughout the thesis, a number of algorithms are developed and simulated using the MATLAB application. This thesis mainly investigates three key issues: First, a novel intelligent NLOS SCB architecture, termed the cognitive NLOS SCB (CNSCB) system is proposed to enable street-to-rooftop NLOS connectivity using predetermined diffraction points located on roof edges. Second, an algorithm to enable the autonomous creation of multiple-paths, evaluate the performance of each link and determine an optimal number of possible paths per backhaul link is developed. Third, an algorithm to determine the optimal number of diffraction points that can cover an identified SCBS location is also developed. Also, another investigated issue related to the operation of the proposed architecture is its energy efficiency, and its performance is compared to that of a point-to-point (PtP) architecture. The proposed solutions were examined using analytical models, simulations and experimental work to determine the strength of the street-to-rooftop backhaul links and their ability to meet current and future SCB requirements. The results obtained showed that reliable multiple NLOS links can be achieved using device intelligence to guide radio signals along the propagation path. Furthermore, the PtMP architecture is found to be more energy efficient than the PtP architecture. The proposed architecture and algorithms offer a novel backhaul solution for outdoor urban small cells. Finally, this research shows that traditional techniques of addressing the demand for connectivity, which consisted of improving or evolving existing solutions, may nolonger be applicable in emerging communication technologies. There is therefore need to consider new ways of solving the emerging challenges

Енергоефективний інтегральний подільник частоти

Дана робота сфокусована на розробці інтегрального подільника частоти на технології The 22FDX GlobalFoundries. В роботі використано три конфігурації подільників частоти для різних частот в діапазоні від 20 ГГц до 10 МГц. Також ця робота містить активний балун для генерації диференційного сигналу та два підсилювачі сигналу. Розробка компаратора була виконана у середовищі Cadence, з використанням наявних функцій та інструментів, які дозволяють підібрати оптимальні компоненти та характеристики пристрою, в повній мірі проаналізувати роботу розробленого пристрою з урахуванням виробничих особливостей, фізичних явищ та технологічних обмежень. Метою даної роботи були мінімальний розмір схем, оптимізація споживання струму при збереженні якісних характеристик роботи схеми. Було проведено аналіз роботи схем, швидкодія, якість вихідного сигналу, споживання струму та чутливість до частоти та амплітуди вхідного сигналу. Кожний параметр був проаналізований в кутовому аналізі, а також після розробки топологічного креслення з урахуванням ємносних та резистивних паразитних компонентів. Топологічні креслення було виконано з урахуванням паразитних явищ (руйнація металів під дією струму, паразитних компонентів між провідниками тощо). Кожна топологія подільника була перевірена на відповідність DRC та LVC з врахуванням технологічних вимог. Загальне споживання електричного струму пристроєм 6-10 мА з урахуванням активного балуна, який споживає 2-4 мА. Було використано 257 польових транзисторів різних конфігурацій, 30 конденсаторів та 14 резисторів. Загальний розмір розробленого блоку на чіпі 510 на 360 мкм.The primary objective of this work is to develop an integral frequency divider based on The 22FDX GlobalFoundries technology. This work contains CML, TSPC and CMOS circuits for high, medium and low frequencies, respectively in the range of 20 GHz to 10 MHz. Also, this work contains an active balun for generating a differential signal and two buffers. The aim was to develop CML frequency divider, that could function on high frequencies in the 40 GHz to 5 GHz range with minimal current consumption and minimal loss of signal power. When conducting research on existing blocks that meet the necessary conditions, the CML design was chosen. Some parts of the existing technology were modified to achieve satisfactory results, such as the control and limiting current source. Usually, CML uses a current source to regulate power consumption. In the case of the developed device, the same current consumption (subject to the same other operating parameters) was at a gate width of 3 μm without a current source, or at 4 μm with a current source. So it was decided to use the so-called pseudo CML without a current source with smaller transistor sizes. When analyzing the developed divider, a graph of sensitivity under different conditions was constructed. From the obtained results, it can be concluded that in case of an extraction simulation with parasitic capacitors and supports, the sensitivity curve narrows, but due to the selected dimensions at the operating frequencies in a specific task, the sensitivity curve retains the best values. When conducting studies of existing blocks that meet the necessary conditions, the TSPC design was chosen. The choice of the particular design was intended to preserve the differential signal from past blocks, maintain amplitude and power, while preventing an increase in current consumption and block size in the topology drawing. This design has a minimum size because it does not contain inductive or capacitive elements, but at the same time it satisfactorily performs the task of a frequency divider in the required range from 5 GHz to 625 MHz. The TSPC unit was designed with negative feedback. The 22FDX® technology allowed adding all transistors with the same type of substrate, which reduces the number of parasitic components during production. During the analysis of the developed divider, satisfactory results of output differential signals, low current consumption (no more than 200 μA), power conservation and speed of operation were obtained. The choice of CMOS design as the last part of the developed device was intended to simplify the frequency divider. At low frequencies, there is no need for powerful transistors, protection against electromagnetic noise, etc. That is, it is necessary to simplify the device as much as possible while maintaining speed, signal quality and current consumption

Cmos Based Lensless Imaging Systems And Support Circuits

While much progress has been made in various fields of study in past few decades, leading to better understanding of science as well as better quality of life, the role of optical sensing has grown among electrical, chemical, optical, and other physical signal modalities. As an example, fluorescent microscopy has become one of the most important methods in the modern biology. However, broader implementation of optical sensing has been limited due to the expensive and bulky optical and mechanical components of conventional optical sensor systems. To address such bottleneck, this dissertation presents several cost-effective, compact approaches of optical sensor arrays based on solid state devices that can replace the conventional components. As an example, in chapter 2 we demonstrate a chip-scale (<1 mm2 ) sensor, the Planar Fourier Capture Array (PFCA), capable of imaging the far-field without any off-chip optics. The PFCA consists of an array of angle-sensitive pixels manufactured in a standard semiconductor process, each of which reports one component of a spatial two-dimensional (2D) Fourier transform of the local light field. Thus, the sensor directly captures 2D Fourier transforms of scenes. The effective resolution of our prototype is approximately 400 pixels. My work on this project [15] includes a circuit design and layout and the overall testing of the imaging system. In chapter 3 we present a fully integrated, Single Photon Avalanche Detector (SPAD) using only standard low- voltage (1.8V) CMOS devices in a 0.18m process. The system requires one highvoltage AC signal which alternately reverse biases the SPADs into avalanche breakdown and then resets with a forward bias. The proposed self-quenching circuit intrinsically suppresses after-pulse effects, improving signal to noise ratio while still permitting fine time resolution. The required high-voltage AC signal can be generated by resonant structures and can be shared across arrays of SPADs [24]. An ideal light sensor to provide the precise incident intensity, location, and angle of incoming photons is shown in chapter 4. Single photon avalanche diodes (SPADs) provide such desired high (single photon) sensitivity with precise time information, and can be implemented at a pixel scale to form an array to extract spatial information. Furthermore, recent work has demonstrated photodiode-based structures (combined with micro-lenses and diffraction gratings) that are capable of encoding both spatial and angular information of the incident light. In this chapter, we describe the implementation of such grating structure on SPAD to realize a pixel-scale angle-sensitive single photon avalanche diode (A-SPAD) using a standard CMOS process. While the underlying SPAD structure provides the high sensitivity, the diffraction gratings consisting of two sets of metal layers offers the angle-sensitivity. Such unique combination of the SPAD and the diffraction gratings expand the sensing dimensions to pave a path towards a lens-less 3-D imaging and a light-field timeof-flight imaging. In chapter 5, we present a 72 x 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3-D fluorescent life time imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, to reject high-powered UV stimulus, and to map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings on top of the SPAD to extract incident angles of incoming light, enabling 3-D localization at a micrometer scale. The chip presented in this work also integrates pixel-level counters as well as shared timing circuitry, and is implemented in conventional 180nm CMOS technology without any post-processing. Contact-based read- out from a revolving MEMS accelerometers is problematic therefore contactless (optical) read-out is preferred. The optical readout requires an image sensor to resolve nanometer-scale shifts of the MEMS image. Traditional imagers record on a rectangular grid which is not well-suited for efficiently imaging rotating objects due to the significant processing overhead required to translate Cartesian coordinates to angular position. Therefore, in chapter 6 we demonstrate a high-speed ( 1kfps), circular, CMOS imaging array for contact-less, optical measurement of rotating inertial sensors. The imager is designed for real-time optical readout and calibration of a MEMS accelerometer revolving at greater than 1000rpm. The imager uses a uniform circular arrangement of pixels to enable rapid imaging of rotational objects. Furthermore, each photodiode itself is circular to maintain uniform response throughout the entire revolution. Combining a high frame rate and a uniform response to motion, the imager can achieve sub-pixel resolution (25nm) of the displacement of micro scale features. In order to avoid fixed pattern noise arising from non-uniform routing within the array we implemented a new global shutter technique that is insensitive to parasitic capacitance. To ease integration with various MEMS platforms, the system has SPI control, on-chip bias generation, sub-array imaging, and digital data read-out. My work on this project [20] includes a circuit design and lay- out and some testing including, a FPGA based controller design of the imaging system. In the previous chapters, compact and cost effective imaging sys- tems have been introduced. Those imaging systems show great potential for wireless implantable systems. A power rectifier for the implant provides a volt- age DC power with a small inductor, for small volume, from a small AC voltage input. In the last chapter we demonstrate an inductively powered, orthogonal current-reuse multi-channel amplifier for power-efficient neural recording. The power rectifier uses the input swing as a self-synchronous charge pump, making it a fully passive, full-wave ladder rectifier. The rectifier supplies 10.37[MICRO SIGN]W at 1.224V to the multi-channel amplifier, which includes bias generation. The prototype device is fabricated in a TSMC 65nm CMOS process, with an active area of 0.107mm2 . The maximum measured power conversion efficiency (PCE) is 16.58% with a 184mV input amplitude. My work on this project [25] in- cludes the rectifier design and overall testing to combine "orthogonal currentreuse neural amplifier" designed by Ben Johnson

Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Low Frequency Noise in CMOS transistors

The minimum measurable signal strength of an electronic system is limited by noise. With the advent of very large scale integrated (VLSI) systems, low power designs are achieved by reducing the supply voltage and the drive current. This reduces the dynamic range of the system. As the signal in an amplifier system is usually set to be a significant fraction of the dynamic range, all other factors being equal, reduction in dynamic range leads to a degradation of the signal to noise ratio (SNR). This thesis addresses this issue in low power design. Focus is given to low frequency (< 1 kHz) noise. This frequency range is dominated by flicker noise, also referred to as pink or 1/f noise. Most biomedical and audio signals lie in this low frequency domain. For example, electrocardiograms (ECGs) record signals which are < 50 Hz. Audio signals have a large portion of signals that lie in the low frequency bandwidth. The focus here is on low-frequency performance of CMOS transistors. This represents a significant challenge in detection as noise in solid state devices tends to increase with decreases in frequency. That is, it becomes ``pink," weighted to the low frequency spectral range. Usually, we find that noise power changes reciprocally with frequency as we reach the kilohertz frequency range. While there has been no single, definitive theory of pink noise, system design principles can be formulated to minimize the impact of this noise. There are two factors to consider here. First, the pink noise process appears to be related to interaction with the defect structure of the solid through which charge is transported. As the number of defects is finite, there is a limit to the number of charges that can interact with this defect population. Thus, there is a limit on the amount of fluctuation in this interaction ``current." This limit depends on the number of defects present in the solid through which transport occurs. It also depends on the number of charges transported. Thus, the trivial and often cited optimization principle demanding a reduced solid defect density presents itself. This leads to a second, less obvious principle of optimization. If the number of transported charges is large, and the trap defect parameters (number density, cross-section, trap lifetime, etc.) does not depend on total current passed, it is possible to ``overcome" the defect-related noise. This is done by increasing the bias current. For fixed defect density, increased bias current will ``saturate" the 1/f-noise fluctuation at some level resulting in an increase in SNR. Large current leads to large power dissipation, an undesirable side-effect of saturating the 1/f-noise current. This problem of SNR and power optimization has been addressed in this work. The main contribution of the work is development of an analog design methodology utilizing saturation effect to improve system SNR through bias optimization. Flicker noise measurement was carried out for the low frequency region in 0.5um and 130 nm CMOS process and SNR studied under different gate bias voltages. We further investigated the impact of size variation, radiation stress and hot electron injection on the optimal bias point of the device. In addition, low temperature noise spectroscopy was conducted to study the noise behavior. Double channel method was used which enabled measurement of pink noise at very low gate biases. The work investigates signal, noise and power in deep-subthreshold region for the first time

Bio-inspired electronics for micropower vision processing

Vision processing is a topic traditionally associated with neurobiology; known to encode, process and interpret visual data most effectively. For example, the human retina; an exquisite sheet of neurobiological wetware, is amongst the most powerful and efficient vision processors known to mankind. With improving integrated technologies, this has generated considerable research interest in the microelectronics community in a quest to develop effective, efficient and robust vision processing hardware with real-time capability. This thesis describes the design of a novel biologically-inspired hybrid analogue/digital vision chip ORASIS1 for centroiding, sizing and counting of enclosed objects. This chip is the first two-dimensional silicon retina capable of centroiding and sizing multiple objects2 in true parallel fashion. Based on a novel distributed architecture, this system achieves ultra-fast and ultra-low power operation in comparison to conventional techniques. Although specifically applied to centroid detection, the generalised architecture in fact presents a new biologically-inspired processing paradigm entitled: distributed asynchronous mixed-signal logic processing. This is applicable to vision and sensory processing applications in general that require processing of large numbers of parallel inputs, normally presenting a computational bottleneck. Apart from the distributed architecture, the specific centroiding algorithm and vision chip other original contributions include: an ultra-low power tunable edge-detection circuit, an adjustable threshold local/global smoothing network and an ON/OFF-adaptive spiking photoreceptor circuit. Finally, a concise yet comprehensive overview of photodiode design methodology is provided for standard CMOS technologies. This aims to form a basic reference from an engineering perspective, bridging together theory with measured results. Furthermore, an approximate photodiode expression is presented, aiming to provide vision chip designers with a basic tool for pre-fabrication calculations