1,404 research outputs found

    Cloud Computing cost and energy optimization through Federated Cloud SoS

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    2017 Fall.Includes bibliographical references.The two most significant differentiators amongst contemporary Cloud Computing service providers have increased green energy use and datacenter resource utilization. This work addresses these two issues from a system's architectural optimization viewpoint. The proposed approach herein, allows multiple cloud providers to utilize their individual computing resources in three ways by: (1) cutting the number of datacenters needed, (2) scheduling available datacenter grid energy via aggregators to reduce costs and power outages, and lastly by (3) utilizing, where appropriate, more renewable and carbon-free energy sources. Altogether our proposed approach creates an alternative paradigm for a Federated Cloud SoS approach. The proposed paradigm employs a novel control methodology that is tuned to obtain both financial and environmental advantages. It also supports dynamic expansion and contraction of computing capabilities for handling sudden variations in service demand as well as for maximizing usage of time varying green energy supplies. Herein we analyze the core SoS requirements, concept synthesis, and functional architecture with an eye on avoiding inadvertent cascading conditions. We suggest a physical architecture that diminishes unwanted outcomes while encouraging desirable results. Finally, in our approach, the constituent cloud services retain their independent ownership, objectives, funding, and sustainability means. This work analyzes the core SoS requirements, concept synthesis, and functional architecture. It suggests a physical structure that simulates the primary SoS emergent behavior to diminish unwanted outcomes while encouraging desirable results. The report will analyze optimal computing generation methods, optimal energy utilization for computing generation as well as a procedure for building optimal datacenters using a unique hardware computing system design based on the openCompute community as an illustrative collaboration platform. Finally, the research concludes with security features cloud federation requires to support to protect its constituents, its constituents tenants and itself from security risks

    Variable length pattern coding for power reduction in off-chip data buses

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    Off-chip buses consume a huge fraction (20%-40%) of the system power. Hence, techniques such as increasing bus widths, transition encoding etc. have been used for power reduction on off-chip data buses. Since capacitances at the I/O pads and interwire capacitances contribute significantly to increase in power, encoding/decoding schemes have been developed to reduce switching activity of the off-chip bus lines, thus reducing power. Frequent-Value Encoding(FVE) [1], Frequent Value Encoding with Xor (FVExor) [1] and VALVE [2] are some of the better known encoding schemes but they still have scope for improvement. This thesis addresses the problem of power reduction in off-chip data buses by encoding variable number (1 to 4) of fixed-size (32-bit) data values (variable length patterns) which exhibit temporal locality. This characteristic enables us to cache these patterns using 64-entry CAM at the encoder and 64-entry SRAM at the decoder. Whenever a pattern match occurs a 2-bit code indicating the index of the match is sent. If a variable length pattern match occurs then the code and unmatched portion of data is sent. We implemented our scheme, Variable Length Pattern Coding (VLPC) for various integer and floating point benchmarks and have seen 6% to 49% encodable patterns in these benchmarks. Based on the experiments on simplescalar and our analysis in MATLAB, we obtained 4.88% to 40.11% reduction in transition activity for SPEC2000 benchmarks such as crafty, swim, mcf, applu, ammp etc. over unencoded data. This is 0.3% to 38.9% higher than that obtained using FVE, FVExor [1] and VALVE [2] encoding schemes. Finally, we have designed a low-power custom CAM and SRAM using 45nm BSIM4 technology models which has been used to verify lower latency of data matching and storing

    Proactive content caching in future generation communication networks: Energy and security considerations

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    The proliferation of hand-held devices and Internet of Things (IoT) applications has heightened demand for popular content download. A high volume of content streaming/downloading services during peak hours can cause network congestion. Proactive content caching has emerged as a prospective solution to tackle this congestion problem. In proactive content caching, data storage units are used to store popular content in helper nodes at the network edge. This contributes to a reduction of peak traffic load and network congestion. However, data storage units require additional energy, which offers a challenge to researchers that intend to reduce energy consumption up to 90% in next generation networks. This thesis presents proactive content caching techniques to reduce grid energy consumption by utilizing renewable energy sources to power-up data storage units in helper nodes. The integration of renewable energy sources with proactive caching is a significant challenge due to the intermittent nature of renewable energy sources and investment costs. In this thesis, this challenge is tackled by introducing strategies to determine the optimal time of the day for content caching and optimal scheduling of caching nodes. The proposed strategies consider not only the availability of renewable energy but also temporal changes in network trac to reduce associated energy costs. While proactive caching can facilitate the reduction of peak trac load and the integration of renewable energy, cached content objects at helper nodes are often more vulnerable to malicious attacks due to less stringent security at edge nodes. Potential content leakage can lead to catastrophic consequences, particularly for cache-equipped Industrial Internet of Things (IIoT) applications. In this thesis, the concept of \trusted caching nodes (TCNs) is introduced. TCNs cache popular content objects and provide security services to connected links. The proposed study optimally allocates TCNs and selects the most suitable content forwarding paths. Furthermore, a caching strategy is designed for mobile edge computing systems to support IoT task offloading. The strategy optimally assigns security resources to offloaded tasks while satisfying their individual requirements. However, security measures often contribute to overheads in terms of both energy consumption and delay. Consequently, in this thesis, caching techniques have been designed to investigate the trade-off between energy consumption and probable security breaches. Overall, this thesis contributes to the current literature by simultaneously investigating energy and security aspects of caching systems whilst introducing solutions to relevant research problems

    Software and hardware methods for memory access latency reduction on ILP processors

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    While microprocessors have doubled their speed every 18 months, performance improvement of memory systems has continued to lag behind. to address the speed gap between CPU and memory, a standard multi-level caching organization has been built for fast data accesses before the data have to be accessed in DRAM core. The existence of these caches in a computer system, such as L1, L2, L3, and DRAM row buffers, does not mean that data locality will be automatically exploited. The effective use of the memory hierarchy mainly depends on how data are allocated and how memory accesses are scheduled. In this dissertation, we propose several novel software and hardware techniques to effectively exploit the data locality and to significantly reduce memory access latency.;We first presented a case study at the application level that reconstructs memory-intensive programs by utilizing program-specific knowledge. The problem of bit-reversals, a set of data reordering operations extensively used in scientific computing program such as FFT, and an application with a special data access pattern that can cause severe cache conflicts, is identified in this study. We have proposed several software methods, including padding and blocking, to restructure the program to reduce those conflicts. Our methods outperform existing ones on both uniprocessor and multiprocessor systems.;The access latency to DRAM core has become increasingly long relative to CPU speed, causing memory accesses to be an execution bottleneck. In order to reduce the frequency of DRAM core accesses to effectively shorten the overall memory access latency, we have conducted three studies at this level of memory hierarchy. First, motivated by our evaluation of DRAM row buffer\u27s performance roles and our findings of the reasons of its access conflicts, we propose a simple and effective memory interleaving scheme to reduce or even eliminate row buffer conflicts. Second, we propose a fine-grain priority scheduling scheme to reorder the sequence of data accesses on multi-channel memory systems, effectively exploiting the available bus bandwidth and access concurrency. In the final part of the dissertation, we first evaluate the design of cached DRAM and its organization alternatives associated with ILP processors. We then propose a new memory hierarchy integration that uses cached DRAM to construct a very large off-chip cache. We show that this structure outperforms a standard memory system with an off-level L3 cache for memory-intensive applications.;Memory access latency has become a major performance bottleneck for memory-intensive applications. as long as DRAM technology remains its most cost-effective position for making main memory, the memory performance problem will continue to exist. The studies conducted in this dissertation attempt to address this important issue. Our proposed software and hardware schemes are effective and applicable, which can be directly used in real-world memory system designs and implementations. Our studies also provide guidance for application programmers to understand memory performance implications, and for system architects to optimize memory hierarchies

    Towards self-powered wireless sensor networks

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    Ubiquitous computing aims at creating smart environments in which computational and communication capabilities permeate the word at all scales, improving the human experience and quality of life in a totally unobtrusive yet completely reliable manner. According to this vision, an huge variety of smart devices and products (e.g., wireless sensor nodes, mobile phones, cameras, sensors, home appliances and industrial machines) are interconnected to realize a network of distributed agents that continuously collect, process, share and transport information. The impact of such technologies in our everyday life is expected to be massive, as it will enable innovative applications that will profoundly change the world around us. Remotely monitoring the conditions of patients and elderly people inside hospitals and at home, preventing catastrophic failures of buildings and critical structures, realizing smart cities with sustainable management of traffic and automatic monitoring of pollution levels, early detecting earthquake and forest fires, monitoring water quality and detecting water leakages, preventing landslides and avalanches are just some examples of life-enhancing applications made possible by smart ubiquitous computing systems. To turn this vision into a reality, however, new raising challenges have to be addressed, overcoming the limits that currently prevent the pervasive deployment of smart devices that are long lasting, trusted, and fully autonomous. In particular, the most critical factor currently limiting the realization of ubiquitous computing is energy provisioning. In fact, embedded devices are typically powered by short-lived batteries that severely affect their lifespan and reliability, often requiring expensive and invasive maintenance. In this PhD thesis, we investigate the use of energy-harvesting techniques to overcome the energy bottleneck problem suffered by embedded devices, particularly focusing on Wireless Sensor Networks (WSNs), which are one of the key enablers of pervasive computing systems. Energy harvesting allows to use energy readily available from the environment (e.g., from solar light, wind, body movements, etc.) to significantly extend the typical lifetime of low-power devices, enabling ubiquitous computing systems that can last virtually forever. However, the design challenges posed both at the hardware and at the software levels by the design of energy-autonomous devices are many. This thesis addresses some of the most challenging problems of this emerging research area, such as devising mechanisms for energy prediction and management, improving the efficiency of the energy scavenging process, developing protocols for harvesting-aware resource allocation, and providing solutions that enable robust and reliable security support. %, including the design of mechanisms for energy prediction and management, improving the efficiency of the energy harvesting process, the develop of protocols for harvesting-aware resource allocation, and providing solutions that enable robust and reliable security support

    Future Transportation

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    Greenhouse gas (GHG) emissions associated with transportation activities account for approximately 20 percent of all carbon dioxide (co2) emissions globally, making the transportation sector a major contributor to the current global warming. This book focuses on the latest advances in technologies aiming at the sustainable future transportation of people and goods. A reduction in burning fossil fuel and technological transitions are the main approaches toward sustainable future transportation. Particular attention is given to automobile technological transitions, bike sharing systems, supply chain digitalization, and transport performance monitoring and optimization, among others
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