357 research outputs found
Chaotic memristor
We suggest and experimentally demonstrate a chaotic memory resistor
(memristor). The core of our approach is to use a resistive system whose
equations of motion for its internal state variables are similar to those
describing a particle in a multi-well potential. Using a memristor emulator,
the chaotic memristor is realized and its chaotic properties are measured. A
Poincar\'{e} plot showing chaos is presented for a simple nonautonomous circuit
involving only a voltage source directly connected in series to a memristor and
a standard resistor. We also explore theoretically some details of this system,
plotting the attractor and calculating Lyapunov exponents. The multi-well
potential used resembles that of many nanoscale memristive devices, suggesting
the possibility of chaotic dynamics in other existing memristive systems.Comment: Applied Physics A (in press
On the validity of memristor modeling in the neural network literature
An analysis of the literature shows that there are two types of
non-memristive models that have been widely used in the modeling of so-called
"memristive" neural networks. Here, we demonstrate that such models have
nothing in common with the concept of memristive elements: they describe either
non-linear resistors or certain bi-state systems, which all are devices without
memory. Therefore, the results presented in a significant number of
publications are at least questionable, if not completely irrelevant to the
actual field of memristive neural networks
A Compact CMOS Memristor Emulator Circuit and its Applications
Conceptual memristors have recently gathered wider interest due to their
diverse application in non-von Neumann computing, machine learning,
neuromorphic computing, and chaotic circuits. We introduce a compact CMOS
circuit that emulates idealized memristor characteristics and can bridge the
gap between concepts to chip-scale realization by transcending device
challenges. The CMOS memristor circuit embodies a two-terminal variable
resistor whose resistance is controlled by the voltage applied across its
terminals. The memristor 'state' is held in a capacitor that controls the
resistor value. This work presents the design and simulation of the memristor
emulation circuit, and applies it to a memcomputing application of maze solving
using analog parallelism. Furthermore, the memristor emulator circuit can be
designed and fabricated using standard commercial CMOS technologies and opens
doors to interesting applications in neuromorphic and machine learning
circuits.Comment: Submitted to International Symposium of Circuits and Systems (ISCAS)
201
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