±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers

Reduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high-performance capacitance multiplier able to operate with supplies as low as ±0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180-nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300-nW static power dissipation when operating with ±0.25-V supplies

JPL preferred parts list: Reliable electronic components

The JPL Preferred Parts List was prepared to provide a basis for selection of electronic parts for JPL spacecraft programs. Supporting tests for the listed parts were designed to comply with specific spacecraft environmental requirements. The list tabulates the electronic, magnetic, and electromechanical parts applicable to all JPL electronic equipment wherein reliability is a major concern. The parts listed are revelant to equipment supplied by subcontractors as well as fabricated at the laboratory

360 nW gate-driven ultra-low voltage CMOS linear transconductor with 1 MHz bandwidth and wide input range

A low voltage linear transconductor is introduced. The circuit is a pseudo differential architecture that operates with ±0.2V supplies and uses 900nA total biasing current. It employs a floating battery technique to achieve low voltage operation. The transconductor has a 1MHz bandwidth. It exhibits a SNR = 72dB, SFDR = 42dB and THD = 0.83% for a 100mVpp 10kHz sinusoidal input signal. Moreover, stability is not affected by the capacitance of the signal source. The circuit has been validated with a prototype chip fabricated in a 130nm CMOS technology.This work was supported in part by the Agencia Estatal de Investigacion/Fondo Europeo de Desarrollo Regional under Grant TEC2016-80396-C2. The work of Hector D. Rico-Aniles was supported by the Mexican Consejo Nacional de Ciencia y Tecnologia for the through an Academic Scholarship under Grant 408946

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Circuits for Analog Signal Processing Employing Unconventional Active Elements

Disertační práce se zabývá zaváděním nových struktur moderních aktivních prvků pracujících v napěťovém, proudovém a smíšeném režimu. Funkčnost a chování těchto prvků byly ověřeny prostřednictvím SPICE simulací. V této práci je zahrnuta řada simulací, které dokazují přesnost a dobré vlastnosti těchto prvků, přičemž velký důraz byl kladen na to, aby tyto prvky byly schopny pracovat při nízkém napájecím napětí, jelikož poptávka po přenosných elektronických zařízeních a implantabilních zdravotnických přístrojích stále roste. Tyto přístroje jsou napájeny bateriemi a k tomu, aby byla prodloužena jejich životnost, trend navrhování analogových obvodů směřuje k stále většímu snižování spotřeby a napájecího napětí. Hlavním přínosem této práce je návrh nových CMOS struktur: CCII (Current Conveyor Second Generation) na základě BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na základě FG, transkonduktor na základě nové techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na základě GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na základě GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na základě BD. Dále je uvedeno několik zajímavých aplikací užívajících výše jmenované prvky. Získané výsledky simulací odpovídají teoretickým předpokladům.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.

The Conference on High Temperature Electronics

The status of and directions for high temperature electronics research and development were evaluated. Major objectives were to (1) identify common user needs; (2) put into perspective the directions for future work; and (3) address the problem of bringing to practical fruition the results of these efforts. More than half of the presentations dealt with materials and devices, rather than circuits and systems. Conference session titles and an example of a paper presented in each session are (1) User requirements: High temperature electronics applications in space explorations; (2) Devices: Passive components for high temperature operation; (3) Circuits and systems: Process characteristics and design methods for a 300 degree QUAD or AMP; and (4) Packaging: Presently available energy supply for high temperature environment

CMOS indoor light energy harvesting system for wireless sensing applications

Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de ComputadoresThis research thesis presents a micro-power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched-capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT Fractional Open Circuit Voltage (VOC) technique is implemented by an asynchronous state machine (ASM) that creates and, dynamically, adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point (MPP) condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge reusing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm2 in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm2, is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m2. After starting-up, the system requires an irradiance of only 0.18 W/m2 (18 mW/cm2) to remain in operation. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3% for an input power of 48 mW, which is comparable with reported values from circuits operating at similar power levels.Portuguese Foundation for Science and Technology (FCT/MCTES), under project PEst-OE/EEI/UI0066/2011, and to the CTS multiannual funding, through the PIDDAC Program funds. I am also very grateful for the grant SFRH/PROTEC/67683/2010, financially supported by the IPL – Instituto Politécnico de Lisboa