Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study

In this paper, we present a detailed simulation study of the influence of quantum mechanical effects in the inversion layer on random dopant induced threshold voltage fluctuations and lowering in sub-100 mn MOSFETs. The simulations have been performed using a three-dimensional (3-D) implementation of the density gradient (DG) formalism incorporated in our established 3-D atomistic simulation approach. This results in a self-consistent 3-D quantum mechanical picture, which implies not only the vertical inversion layer quantization but also the lateral confinement effects related to current filamentation in the “valleys” of the random potential fluctuations. We have shown that the net result of including quantum mechanical effects, while considering statistical dopant fluctuations, is an increase in both threshold voltage fluctuations and lowering. At the same time, the random dopant induced threshold voltage lowering partially compensates for the quantum mechanical threshold voltage shift in aggressively scaled MOSFETs with ultrathin gate oxides

LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS

Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the \uf07e105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress simulation shows that the oval air gaps around the SiO2 template can reduce the thermal stress by 50% and help reduce the DD. We have then compared the structural and electrical characteristics of n-type Ge films with its p-type counter parts. In n-type Ge, the DD decreases from \uf07e109cm-2 near the Ge-Si interface to \uf07e105 cm-2 at the film surface. In contrast, we observe 5\uf0b4107 cm-2 TDD at the film surface in p-type Ge. The full width at half-maximum for our n-type Ge(004) XRD peak is ~70% narrower than that of p-type Ge. As a stringent test of the dislocation reduction, we have also fabricated and characterized high-carrier-mobility MOSFETs on GoS substrates. We also report p- and n-MOSFETs with μeff of 401 and 940 cm2/V-s and a subthreshold slope of 100 and 200 mV/decade, respectively. These effective mobilities show an exceptional 82 and 30% improvement over that of conventional Si channel MOSFETs. We also investigate the optical quality of ultra-low DD GoS film by measuring photoluminescence (PL). The n-type Ge PL main peak shows pronounced tensile-strain (x0.8%) than that of p-type which is an indicator of direct BG shrinking at the \u0413 band-edge. Going beyond epitaxial engineering and device fabrication, we have also recently demonstrated a scalable path to create a 2D array of Ge quantum dots (QDs) on responsive SiGe substrates based on elastic mechanical deformation and subsequent SiGe compositional redistribution, coupled with MBE growth. For large-scale manufacturing of single-electron transistors, we have also demonstrated that a spatially structured elastic compressive stress to the SiGe substrate with thermally annealing leads to a compositional redistribution of Si and Ge in the near-surface region of SiGe substrates, forming a 2D array of Ge-depleted nanoscale regions. Based on these latest findings, we have also begun to chart a future direction for my research group, where one can explore new advanced device architectures, such as Si-compatible, optically actuated, Ge-quantum dot-based field effect transistors

Assessment of High-Frequency Performance Limit of Black Phosphorus Field-Effect Transistors

© 2017 IEEE.Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Recently gigahertz frequencies have been reported with black phosphorus (BP) field-effect transistors (FETs), yet the high-frequency performance limit has remained unexplored. Here we project the frequency limit of BP FETs based on rigorous atomistic quantum transport simulations and the small-signal circuit model. Our self-consistent non-equilibrium Green’s function (NEGF) simulation results show that semiconducting BP FETs exhibit clear saturation behaviors with the drain voltage, unlike zero-bandgap graphene devices, leading to >10 THz frequencies for both intrinsic cutoff frequency (fT) and unity power gain frequency (fmax). To develop keen insight into practical devices, we discuss the optimization of fT and fmax by varying various device parameters such as channel length (Lch), oxide thickness, device width, gate resistance, contact resistance and parasitic capacitance. Although extrinsic fT and fmax can be significantly affected by the contact resistance and parasitic capacitance, they can remain near THz frequency range (fT = 900 GHz; fmax = 1.2 THz) through proper engineering, particularly with an aggressive channel length scaling (Lch ≈ 10 nm). Our benchmark against the experimental data indicates that there still exists large room for optimization in fabrication, suggesting further advancement of high-frequency performance of state-of-the-art BP FETs for the future analogue and radio-frequency applications.NSERC RGPIN-05920-2014 and STPGP 478974-1

Physics and Technology of Silicon Carbide Devices

Recently, some SiC power devices such as Schottky-barrier diodes (SBDs), metal-oxide-semiconductor field-effect-transistors (MOSFETs), junction FETs (JFETs), and their integrated modules have come onto the market. However, to stably supply them and reduce their cost, further improvements for material characterizations and those for device processing are still necessary. This book abundantly describes recent technologies on manufacturing, processing, characterization, modeling, and so on for SiC devices. In particular, for explanation of technologies, I was always careful to argue physics underlying the technologies as much as possible. If this book could be a little helpful to progress of SiC devices, it will be my unexpected happiness

Methods for the atomistic simulation of ultrasmall semiconductor devices

As the feature sizes in VLSI technology shrink to less than 100 nm the effects due to the quantisation of electronic charge begin to emerge. There are a small number of carriers and impurities and the statistical variation in their number have significant effects on the threshold characteristics of the devices that hamper their large scale integration into future ULSI.The complex potential landscape arising from the Coulomb force, with its sharp localised peaks and troughs, faces problems due to band limiting in meshes and places heavy burdens on the integration techniques. A computationally efficient solution to the problem of band-limiting is presented and is shown to provide an accurate description of the electrostatics. This work also introduces a highly efficient and numerically stable multigrid solver, for Poisson's equation, that can cope with the complex potential distributions on large meshes.The study of ionised impurity scattering is used to validate these molecular dynamics simulations. Results have shown that the Brownian method - despite precluding the use of adaptive integration schemes - gives a good approximation to the standard results and has the advantage of smoothing away errors that can build up during the integration of motion and drives the system towards thermal equilibrium.The greatest hurdle to be cleared before these three-dimensional simulations can be practicable is the sheer computational effort that is required. The implementation of the problem on parallel architectures has been explored and discussed.The methods developed in this work are demonstrated through the simulation of an 80 nm dual-gate MESFET. The results were verified by comparing them with those from a commercial drift-diffusion simulator.The threshold behaviour of devices has been investigated through the study of the formation of conduction channels in blocks. The percolation threshold gives the point when conductive paths form across the gate barrier. The results from the FET simulation were found to be in agreement with the earlier studies on the blocks

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

1996 Laboratory directed research and development annual report

This report summarizes progress from the Laboratory Directed Research and Development (LDRD) program during fiscal year 1996. In addition to a programmatic and financial overview, the report includes progress reports from 259 individual R&D projects in seventeen categories. The general areas of research include: engineered processes and materials; computational and information sciences; microelectronics and photonics; engineering sciences; pulsed power; advanced manufacturing technologies; biomedical engineering; energy and environmental science and technology; advanced information technologies; counterproliferation; advanced transportation; national security technology; electronics technologies; idea exploration and exploitation; production; and science at the interfaces - engineering with atoms

THERMAL HEAT TRANSPORT AT THE NANO-SCALE LEVEL AND ITS APPLICATION TO NANO-MACHINING

Nano-manufacturing is receiving significant attention in industry due to the ever-growing interest in nanotechnology in research institutions. It is hypothesized that single-step or direct-write nano-scale machining might be achieved by coupling nano-probe field emission with radiation transfer. A laser may be used to heat a workpiece within a microscopic region that encloses an even smaller nanoscopic region subjected to a focused electron beam. The electron-beam supplies marginal heat sufficient to remove a minute volume of material by evaporation or sublimation. Experimentally investigating this hypothesis requires an estimate of the power needed in the electron-beam. To this end, a detailed numerical study is conducted to study the possibility of using the nano-probe field emission for nano-machining. The modeling effort in this case is divided into two parts. The first part deals with the electron-beam propagation inside a target workpiece. The second part considers the temperature increase due to the energy transfer between the electron-beam and the workpiece itself. A Monte Carlo/Ray Tracing technique is used in modeling the electron-beam propagation. This approach is identical to that of a typical Monte Carlo simulation in radiative transfer, except that proper electron scattering properties are employed. The temperature distribution inside a gold film is predicted using the heat conduction equations. Details of the various numerical models employed in the simulation and a series of representative results will be presented in this dissertation

Report / Institute für Physik

The 2016 Report of the Physics Institutes of the Universität Leipzig presents a hopefully interesting overview of our research activities in the past year. It is also testimony of our scientific interaction with colleagues and partners worldwide. We are grateful to our guests for enriching our academic year with their contributions in the colloquium and within our work groups