Studies on Implementation of . . . High Throughput and Low Power Consumption

In this thesis we discuss design and implementation of frequency selective digital filters with high throughput and low power consumption. The thesis includes proposed arithmetic transformations of lattice wave digital filters that aim at increasing the throughput and reduce the power consumption of the filter implementation. The thesis also includes two case studies where digital filters with high throughput and low power consumption are required. A method for obtaining high throughput as well as reduced power consumption of digital filters is arithmetic transformation of the filter structure. In this thesis arithmetic transformations of first- and second-order Richards’ allpass sections composed by symmetric two-port adaptors and implemented using carry-save arithmetic are proposed. Such filter sections can be used for implementation of lattice wave digital filters and bireciprocal lattice wave digital filters. The latter structures are efficient for implementation of interpolators and decimators by factors of two. Th

Evolutionary Design Method of Multipliers Using Development

Tato práce je zaměřena na techniky překonání problému škálovatelnosti při evolučním návrhu kombinačních násobiček. Běžně používané techniky evolučního návrhu pracují přímo s kandidátním řešením, což není příliš vhodné při návrhu rozsáhlých struktur. Je zde použita technika developmentu, která zajišťuje netriviální mapování genotypu na fenotyp. Pomocí developmentu založeného na instrukcích jsme schopni vytvořit poměrně rozsáhlé obvody. V práci jsou představeny tři modely pro tvoření násobičky, která jako poslední stupeň obvodu pro výpočet finálního součtu využívá sčítačku s postupným přenosem.This work is focused on the techniques for overcoming the problem of scale in the evolutionary design of the combinational multipliers. The approaches to the evolutionary design that work directly with the target solutions are not suitable for the design of the large-scale structures. An approach based on the biological principles of development has often been utilized as a non-trivial genotypephenotype mapping in the evolutionary algorithms that allows us to design scalable structures. The instruction-based developmental approach has been applied to the evolutionary design of generic circuit structures. In this work, three methods are presented for the construction of the combinational multipliers which use a ripple-carry adder for obtaining the final product.

Design and Silicon Area Optimization of Time-Domain GNSS Receiver Baseband Architectures

The use of Global Navigation Satellite Systems (GNSSs) in a wide range of portable devices has exploded in the recent years. Demands for a lower cost while expecting longer battery life and better performance are constantly increasing. The general GNSS receiver operation and algorithms are already well studied in the literature, but the hardware architectures and designs have not been discussed in detail.This thesis introduces a high level gate count estimation method that provides good accuracy without requiring the hardware being fully specified. It is based on developing hierarchical models, which are parameterizable, while requiring minimal amount of information about the silicon technology used for the implementation. The average accuracy has been shown to be 4%.Three time-domain, real-time GNSS receiver baseband architectures are described with a discussion about various optimization methods for efficient implementation: the correlator, the matched filter, and the group correlator, which is a new architecture combining some of the features of the two first ones.Four use cases are defined for different GNSS operating modes: Acquisition, tracking, assisted GNSS, and the combination of the first three modes. A comparison is made for receiver basebands including all necessary blocks for full functionality to find out which of the three architectures provides the most silicon area efficient implementation.It is shown that the correlator offers good flexibility, but yields the highest silicon area for acquisition use cases. The matched filter is best suited for the acquisition, but has large overhead when it comes to tracking the signals. The group correlator offers a reasonably good flexibility and area efficiency in all use cases.The main contributions of the thesis are: Development of domain specific optimizations for GNSS receivers and an accurate gate count estimation method, which are applied for a quantitative comparison of different GNSS receiver architectures. The results show that no single architecture excels in all cases, and the best choice depends on the actual use case

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing