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    Soft lithography molding of polymer integrated optical devices: Reduction of the background residue

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    Soft lithography molding is a promising technique for patterning polymer integrated optical devices, however the presence of a background residue has the potential to limit the usefulness of this technique. We present the soft lithography technique for fabricating polymer waveguides. Several effects of the background residue are investigated numerically, including the modal properties of an individual waveguide, the coupling ratio of a directional coupler, and the radiation loss in a waveguide bend. Experimentally, the residue is found to be reduced through dilution of the core polymer solution. We find that the force with which the soft mold is depressed on the substrate does not appreciably affect the waveguide thickness or the residue thickness. Optical microscope images show that the residue is thinnest next to the waveguide

    Decomposition of residue currents

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    Given a submodule JO0rJ\subset \mathcal O_0^{\oplus r} and a free resolution of JJ one can define a certain vector valued residue current whose annihilator is JJ. We make a decomposition of the current with respect to Ass(J)(J) that correspond to a primary decomposition of JJ. As a tool we introduce a class of currents that includes usual residue and principal value currents; in particular these currents admit a certain type of restriction to analytic varieties and more generally to constructible sets

    Pipelined Two-Operand Modular Adders

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    Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The design of pipelined TOMAs is usually obtained by inserting an appriopriate number of latch layers inside a nonpipelined TOMA structure. Hence their area is also determined by the number of latches and the delay by the number of latch layers. In this paper we propose a new pipelined TOMA that is based on a new TOMA, that has the smaller area and smaller delay than other known structures. Comparisons are made using data from the very large scale of integration (VLSI) standard cell library
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