A digitally controlled threshold adjustment circuit in a 0.13um SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13µm SiGe BiCMOS technology and a threshold tunable between ±160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a data rate of up to 80Gbps can be achieved

A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages

Inverse Alexander phase detector

An improved bang-bang phase detector (PD) for multi Gb/s clock and data recovery (CDR) circuits is presented. The proposed PD is based on inverting the Alexander PD. In a typical subsampled CDR circuit, this Inverse Alexander PD results in a ten times better bit error rate (BER) compared with the conventional Alexander PD. Additionally, in the case of duty-cycle distorted input data, this Inverse Alexander PD can even reach 20 times better BER compared with the conventional Alexander PD

Solutions for a single carrier 40 Gbit/s downstream long-reach passive optical network

This paper presents a single carrier 40 Gbit/s downstream long-reach passive optical network (LR-PON) topology as candidate for upgrading cur rent f ber infrastructure towards higher data rates. A 100 km LR-PON network was investigated and 2 solutions to overcome chromatic dispersion were proposed. Firstly, a dispersion compensated element is added to compensate the mean length of the feeder f ber. Secondly, an advanced modulation scheme, i.e. 3-level electrical duo-binary is introduced. This scheme has the advantage of allowing lower bandwidth APDs and requires only limited additional electronics. Furthermore, to overcome the inherent discrepancy between aggregated line rate and user rate, and hence the reduced power effciency, the BiPON protocol is added to minimize signal processing at the high line rates

Fast H.264 intra prediction for network video processing

This letter proposes a fast parallel and deeply pipelined architecture for realtime H. 264 intra 4x4 prediction capable of handling up to 32 High Definition video streams (1920x1080 @ 30 fps) simultaneously, while offering high flexibility and consuming only a fraction of resources available on modern FPGA's. The design has been validated on target using a state of the art Altera Stratix IV FPGA

Statistical approach for human electromagnetic exposure assessment in future wireless ATTO-cell networks

In this article, we study human electromagnetic exposure to the radiation of an ultra dense network of nodes integrated in a floor denoted as ATTO-cell floor, or ATTO-floor. ATTO-cells are a prospective 5 G wireless networking technology, in which humans are exposed by several interfering sources. To numerically estimate this exposure we propose a statistical approach based on a set of finite difference time domain simulations. It accounts for variations of antenna phases and makes use of a large number of exposure evaluations, based on a relatively low number of required simulations. The exposure was expressed in peak-spatial 10-g SAR average (psSAR(10g)). The results show an average exposure level of similar to 4.9 mW/kg and reaching 7.6 mW/kg in 5% of cases. The maximum psSAR(10g) value found in the studied numerical setup equals around 21.2 mW/kg. Influence of the simulated ATTO-floor size on the resulting exposure was examined. All obtained exposure levels are far below 4 W/kg ICNIRP basic restriction for general public in limbs (and 20 W/kg basic restriction for occupational exposure), which makes ATTO-floor a potential low-exposure 5 G candidate

Electronic dispersion precompensation of direct-detected NRZ using analog filtering

We demonstrate (in real-time) electrical dispersion compensation in direct detection links using analog transmit side filtering techniques. By this means, we extend the fiber reach using a low complexity solution while avoiding digital preprocessing and digital-to-analog converters (DACs) which are commonly used nowadays. Modulation is done using an IQ MachZehnder modulator (MZM) which allows straightforward compensation of the complex impulse response caused by chromatic dispersion in the fiber. A SiGe BiCMOS 5-tap analog complex finite impulse response (FIR) filter chip and/or a delay between both driving signals of the MZMs is proposed for the filter implementation. Several link experiments are conducted in C-band where transmission up to 60 km of standard single-mode fiber (SSMF) of direct detected 28Gb/s NRZ/OOK is demonstrated. The presented technique can be used in applications where low power consumption is critical

A low power 2 x 28 Gb/s electroabsorption modulator driver array with on-chip duobinary encoding

An integrated 2 x 28 Gb/s dual-channel duobinary driver IC is presented. Each channel has integrated coding blocks, transforming a non-return-to-zero input signal into a 3-level electrical duobinary signal to achieve an optical duobinary modulation. To the best of our knowledge this is the fastest modulator driver including on-chip duobinary encoding and precoding. Moreover, it only consumes 652 mW per channel at a differential output swing of 6 V-pp