A FLEXIBLE HIGH-BANDWIDTH LOW-LATENCY MULTI-PORT MEMORY CONTROLLER

Multi-port memory controllers (MPMCs) have become increasingly important in many modern applications due to the tremendous growth in bandwidth requirement. Many approaches so far have focused on improving either the memory access latency or the bandwidth utilization for specific applications. Moreover, the application systems are likely to require certain adjustments to connect with an MPMC, since the MPMC interface is limited to a single-clock and single-data-width domain. In this paper, we propose efficient techniques to improve the flexibility, latency, and bandwidth of an MPMC. Firstly, MPMC interfaces employ a pair of dual-clock dualport FIFOs at each port, so any multi-clock multi-data-width application system can connect to an MPMC without requiring extra resources. Secondly, memory access latency is significantly reduced because parallel FIFOs temporarily keep the data transfer between the application system and memory. Lastly, a proposed arbitration scheme, namely window-based first-come-first-serve, considerably enhances the bandwidth utilization. Depending on the applications, MPMC can be properly configured by updating several internal configuration registers. The experimental results in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up to 32 concurrent connections at various clocks and data widths. More significantly, achieved bandwidth utilization is approximately 93.2% of the theoretical bandwidth, and the access latency is minimized as compared to previous designs

Characterization of cassava production systems in Vietnam.

Using a nationally representative survey of cassava-growing households in Vietnam and a robust method of varietal identification based on DNA fingerprinting, this paper provides a broad picture of cassava production and socio-economic characteristics of cassava producers in the country. It presents a descriptive analysis of cassava production practices, varietal use, varietal preferences, as well as cassava utilization, and marketing. Results indicate that more than 85% of the cassava area in Vietnam is planted to improved varieties. The average yield at national level is 19 tons per hectare. About 69% of total cassava produced per household is sold as either fresh roots and/or dried chips. The remaining 31% is either for own consumption or for livestock feed. Of all the six regions surveyed, the Southeast is characterized by the most intensive cassava production practices. It also has the largest average cassava area per household, the highest percentage of tractor use, and a higher percentage of fertilizer application on cassava fields. The findings suggest that there are huge challenges for sustainable cassava intensification, specifically in identifying the needs for market diversification, dealing with emerging pests and diseases, and implementing adequate soil management practices. This is particularly challenging in a system that is driven by the need to maximize output with minimum investment. Future research and development should focus on integrated value chain development with multiple actors focusing attention on integrated pest and disease management, seed systems development, breeding for resistance and earliness, and climate change adaptation, among others

ChaCha20–Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3

Transport Layer Security (TLS) provides a secure channel for end-to-end communications in computer networks. The ChaCha20–Poly1305 cipher suite is introduced in TLS 1.3, mitigating the sidechannel attacks in the cipher suites based on the Advanced Encryption Standard (AES). However, the few implementations cannot provide sufficient speed compared to other encryption standards with Authenticated Encryption with Associated Data (AEAD). This paper shows ChaCha20 and Poly1305 primitives. In addition, a compatible ChaCha20–Poly1305 AEAD with TLS 1.3 is implemented with a fault detector to reduce the problems in fragmented blocks. The AEAD implementation reaches 1.4-cycles-per-byte in a standalone core. Additionally, the system implementation presents 11.56-cycles-per-byte in an RISC-V environment using a TileLink bus. The implementation in Xilinx Virtex-7 XC7VX485T Field-Programmable Gate-Array (FPGA) denotes 10,808 Look-Up Tables (LUT) and 3731 Flip-Flops (FFs), represented in 23% and 48% of ChaCha20 and Poly1305, respectively. Finally, the hardware implementation of ChaCha20–Poly1305 AEAD demonstrates the viability of using a different option from the conventional cipher suite based on AES for TLS 1.3

Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA

In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays an essential role in many security applications, such as transport layer security (TLS), internet protocol security (IPsec), and wireless sensor networks (WSNs). The proposed designs of ECC hardware implementation only focus on a single ECC variant and use many resources. These proposals cannot be used for resource-constrained applications or for the devices that need to provide multiple levels of security. This work provides a multi-functional elliptic curve digital signature algorithm (ECDSA) and Edwards-curve digital signature algorithm (EdDSA) hardware implementation. The core can run multiple ECDSA/EdDSA algorithms in a single design. The design consumes fewer resources than the other single-functional design, and is not based on digital signal processors (DSP). The experiments show that the proposed core could run up to 112.2 megahertz with Virtex-7 devices while consuming only 10,259 slices in total

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations. In addition, a hardware implementation can provide the possibility of unifying the functionality with some secure primitive, for example, a true random number generator (TRNG) or a physical unclonable function (PUF). This paper presents a unified PUF-ChaCha20 in a field-programmable gate-array (FPGA) implementation. The problems and solutions of the PUF implementation are described, exploiting the metastability in latches. The Xilinx Artix-7 XC7A100TCSG324-1 FPGA implementation occupies 2416 look-up tables (LUTs) and 1026 flips-flops (FFs), reporting a 3.11% area overhead. The PUF exhibits values of 49.15%, 47.52%, and 99.25% for the average uniformity, uniqueness, and reliability, respectively. Finally, ChaCha20 reports a speed of 0.343 cycles per bit with the unified implementation

A decentralized localization scheme for swarm robotics based on coordinate geometry and distributed gradient descent

In this paper, a decentralized localization scheme using coordinate geometry and distributed gradient descent (DGD) algorithm is presented. Coordinate geometry is proposed to provide a rough estimation of robots’ location instead of the traditional trigonometry approach, which suffers from flip and discontinuous flex ambiguity. Then, these estimations will be used as initial values for DGD algorithm to determine robots’ real position. Evaluated results on real mobile robots show an average mean error of 2.56 cm, which is closed to the minimum achievable accuracy of the testing platform (2 cm). For a team of eight robots, the total average run time of the proposed scheme is 66.7 seconds. Finally, its application in swarm robotics is verified by experimenting with a self-assembly algorithm named DASH

A Survey of Post-Quantum Cryptography: Start of a New Race

Information security is a fundamental and urgent issue in the digital transformation era. Cryptographic techniques and digital signatures have been applied to protect and authenticate relevant information. However, with the advent of quantum computers and quantum algorithms, classical cryptographic techniques have been in danger of collapsing because quantum computers can solve complex problems in polynomial time. Stemming from that risk, researchers worldwide have stepped up research on post-quantum algorithms to resist attack by quantum computers. In this review paper, we survey studies in recent years on post-quantum cryptography (PQC) and provide statistics on the number and content of publications, including a literature overview, detailed explanations of the most common methods so far, current implementation status, implementation comparisons, and discussion on future work. These studies focused on essential public cryptography techniques and digital signature schemes, and the US National Institute of Standards and Technology (NIST) launched a competition to select the best candidate for the expected standard. Recent studies have practically implemented the public key encryption/key encapsulation mechanism (PKE/KEM) and digital signature schemes on different hardware platforms and applied various optimization measures based on other criteria. Along with the increasing number of scientific publications, the recent trend of PQC research is increasingly evident and is the general trend in the cryptography industry. The movement opens up a promising avenue for researchers in public key cryptography and digital signatures, especially on algorithms selected by NIST