9 research outputs found

    Ion-Gel-Gated Graphene Optical Modulator with Hysteretic Behavior

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    We propose a graphene-based optical modulator and comprehensively investigate its photonic characteristics by electrically controlling the device with an ion-gel top-gate dielectric. The density of the electrically driven charge carriers in the ion-gel gate dielectric plays a key role in tuning the optical output power of the device. The charge density at the ion-gel–graphene interface is tuned electrically, and the chemical potential of graphene is then changed to control its light absorption strength. The optical behavior of the ion-gel gate dielectric exhibits a large hysteresis which originates from the inherent nature of the ionic gel and the graphene–ion-gel interface and a slow polarization response time of ions. The photonic device is applicable to both TE- and TM-polarized light waves, covering two entire optical communication bands, the O-band (1.26–1.36 μm) and the C-band (1.52–1.565 μm). The experimental results are in good agreement with theoretically simulated predictions. The temporal behavior of the ion-gel–graphene-integrated optical modulator reveals a long-term modulation state because of the relatively low mobility of the ions in the ion-gel solution and formation of the electric double layer in the graphene–ion-gel interface. Fast dynamic recovery is observed by applying an opposite voltage gate pulse. This study paves the way to the understanding of the operational principles and future applications of ion-gel-gated graphene optical devices in photonics

    Monolithic Metal Oxide Transistors

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    We devised a simple transparent metal oxide thin film transistor architecture composed of only two component materials, an amorphous metal oxide and ion gel gate dielectric, which could be entirely assembled using room-temperature processes on a plastic substrate. The geometry cleverly takes advantage of the unique characteristics of the two components. An oxide layer is metallized upon exposure to plasma, leading to the formation of a monolithic source–channel–drain oxide layer, and the ion gel gate dielectric is used to gate the transistor channel effectively at low voltages through a coplanar gate. We confirmed that the method is generally applicable to a variety of sol–gel-processed amorphous metal oxides, including indium oxide, indium zinc oxide, and indium gallium zinc oxide. An inverter NOT logic device was assembled using the resulting devices as a proof of concept demonstration of the applicability of the devices to logic circuits. The favorable characteristics of these devices, including (i) the simplicity of the device structure with only two components, (ii) the benign fabrication processes at room temperature, (iii) the low-voltage operation under 2 V, and (iv) the excellent and stable electrical performances, together support the application of these devices to low-cost portable gadgets, <i>i.e</i>., cheap electronics

    Defect-Free Copolymer Gate Dielectrics for Gating MoS<sub>2</sub> Transistors

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    In this study, the poly­(2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane-<i>co</i>-cyclohexyl methacrylate) [p­(V4D4-<i>co</i>-CHMA)] copolymer was developed for use as a gate dielectric in molybdenum disulfide (MoS<sub>2</sub>) field-effect transistors (FETs). The p­(V4D4-<i>co</i>-CHMA) copolymer was synthesized via the initiated chemical vapor deposition (<i>i</i>CVD) of two types of monomers: 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane (V4D4) and cyclohexyl methacrylate (CHMA). Four vinyl groups of V4D4 monomers and cyclohexyl groups of CHMA monomers were introduced to enhance the electrical strength of gate dielectrics through the formation of a highly crosslinked network and to reduce the charge trap densities at the MoS<sub>2</sub>–dielectric interface, respectively. The <i>i</i>CVD-grown p­(V4D4-<i>co</i>-CHMA) copolymer films yielded a dielectric constant of 2.3 and a leakage current of 3.8 × 10<sup>–11</sup> A/cm<sup>2</sup> at 1 MV/cm. The resulting MoS<sub>2</sub> FETs with p­(V4D4-<i>co</i>-CHMA) gate dielectrics exhibited excellent electrical properties, including an electron mobility of 35.1 cm<sup>2</sup>/V s, a subthreshold swing of 0.2 V/dec, and an on–off current ratio of 2.6 × 10<sup>6</sup>. In addition, the environmental and operational stabilities of MoS<sub>2</sub> FETs with p­(V4D4-<i>co</i>-CHMA) top-gate dielectrics were superior to those of devices with SiO<sub>2</sub> back-gate dielectrics. The use of <i>i</i>CVD-grown copolymer gate dielectrics as demonstrated in this study provides a novel approach to realizing next-generation two-dimensional electronics

    Wafer-Scale Microwire Transistor Array Fabricated via Evaporative Assembly

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    One-dimensional (1D) nano/microwires have attracted significant attention as promising building blocks for various electronic and optical device applications. The integration of these elements into functional device networks with controlled alignment and density presents a significant challenge for practical device applications. Here, we demonstrated the fabrication of wafer-scale microwire field-effect transistor (FET) arrays based on well-aligned inorganic semiconductor microwires (indium-gallium-zinc-oxide (IGZO)) and organic polymeric insulator microwires fabricated via a simple and large-area evaporative assembly technique. This microwire fabrication method offers a facile approach to precisely manipulating the channel dimensions of the FETs. The resulting solution-processed monolithic IGZO microwire FETs exhibited a maximum electron mobility of 1.02 cm<sup>2</sup> V<sup>–1</sup> s<sup>–1</sup> and an on/off current ratio of 1 × 10<sup>6</sup>. The appropriate choice of the polymeric microwires used to define the channel lengths enabled fine control over the threshold voltages of the devices, which were employed to fabricate high-performance depletion-load inverters. Low-voltage-operated microwire FETs were successfully fabricated on a plastic substrate using a high-capacitance ion gel gate dielectric. The microwire fabrication technique involving evaporative assembly provided a facile, effective, and reliable method for preparing flexible large-area electronics

    Piezopotential-Programmed Multilevel Nonvolatile Memory As Triggered by Mechanical Stimuli

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    We report the development of a piezopotential-programmed nonvolatile memory array using a combination of ion gel-gated field-effect transistors (FETs) and piezoelectric nanogenerators (NGs). Piezopotentials produced from the NGs under external strains were able to replace the gate voltage inputs associated with the programming/erasing operation of the memory, which reduced the power consumption compared with conventional memory devices. Multilevel data storage in the memory device could be achieved by varying the external bending strain applied to the piezoelectric NGs. The resulting devices exhibited good memory performance, including a large programming/erasing current ratio that exceeded 10<sup>3</sup>, multilevel data storage of 2 bits (over 4 levels), performance stability over 100 cycles, and stable data retention over 3000 s. The piezopotential-programmed multilevel nonvolatile memory device described here is important for applications in data-storable electronic skin and advanced human-robot interface operations

    Proton-Conductor-Gated MoS<sub>2</sub> Transistors with Room Temperature Electron Mobility of >100 cm<sup>2</sup> V<sup>–1</sup> s<sup>–1</sup>

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    Room temperature electron mobility of >100 cm<sup>2</sup> V<sup>–1</sup> s<sup>–1</sup> is achieved for a few-layer MoS<sub>2</sub> transistor by use of a polyanionic proton conductor as the top-gate dielectric of the device. The use of a proton conductor that inherently exhibits a cationic transport number close to 1 yields unipolar electron transport in the MoS<sub>2</sub> channel. The high mobility value is attributed to the effective formation of an electric double layer by the proton conductor, which facilitates electron injection into the MoS<sub>2</sub> channel, and to the effective screening of the charged impurities in the vicinity of the device channel. Through careful temperature-dependent transistor and capacitor measurements, we also confirm quenching of the phonon modes in the proton-conductor-gated MoS<sub>2</sub> channel, which should also contribute to the achieved high mobility. These devices are then used to assemble a simple resistive-load inverter logic circuit, which can be switched at high frequencies above 1 kHz

    Low-Voltage 2D Material Field-Effect Transistors Enabled by Ion Gel Capacitive Coupling

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    Capacitive coupling between an overlying ion gel electrolyte and an underlying oxide thin film is utilized to substantially suppress the operating voltage of field-effect transistors (FETs) based on two-dimensional (2D) transition metal dichalcogenides and black phosphorus. The coupling of the layers is achieved following device fabrication by laminating an ion gel layer over an oxide-gated 2D FET through solution-casting methods. While the original pristine 2D FET requires tens of volts for gating through the oxide layer, the laminated ion gel layer reduces the operating voltage to below 4 V even when the same underlying substrate is used as the back gate electrode. Moreover, this capacitive coupling approach allows low-voltage operation without compromising the off-current level, which often occurs when ion gel electrolytes are directly employed as the gate dielectric material. This approach can likely be generalized to a wide variety of thin-film FETs as a postfabrication method for reducing operating voltages and power consumption

    Modulation of Quantum Tunneling <i>via</i> a Vertical Two-Dimensional Black Phosphorus and Molybdenum Disulfide p–n Junction

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    Diverse diode characteristics were observed in two-dimensional (2D) black phosphorus (BP) and molybdenum disulfide (MoS<sub>2</sub>) heterojunctions. The characteristics of a backward rectifying diode, a Zener diode, and a forward rectifying diode were obtained from the heterojunction through thickness modulation of the BP flake or back gate modulation. Moreover, a tunnel diode with a precursor to negative differential resistance can be realized by applying dual gating with a solid polymer electrolyte layer as a top gate dielectric material. Interestingly, a steep subthreshold swing of 55 mV/dec was achieved in a top-gated 2D BP–MoS<sub>2</sub> junction. Our simple device architecture and chemical doping-free processing guaranteed the device quality. This work helps us understand the fundamentals of tunneling in 2D semiconductor heterostructures and shows great potential in future applications in integrated low-power circuits
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