Impact of crosstalk into high resistivity silicon substrate on the RF performance of SOI MOSFET

Crosstalk propagation through silicon substrate is a serious limiting factor on the performance of the RF devices and circuits. In this work, substrate crosstalk into high resistivity silicon substrate is experimentally analyzed and the impact on the RF behavior of silicon-on-insulator (SOI) MOS transistors is discussed. The injection of a 10 V peak-to-peak single tone noise signal at a frequency of 3 MHz ( fnoise) generates two sideband tones of *−56 dBm separated by fnoise from the RF output signal of a partially depleted SOI MOSFET at 1 GHz and 4.1 dBm. The efficiency of the introduction of a trap-rich polysilicon layer located underneath the buried oxide (BOX) of the high resistivity (HR) SOI wafer in the reduction of the sideband noise tones is demonstrated. An equivalent circuit to model and analyze the generation of these sideband noise tones is proposed

Small- and large-signal characterization of trap-rich HR-Si/HR-SOI wafers for SoC applications

For the last five years the semiconductor industry has evolved from a quest to get more logic and computational power to one that looks for more performance, more functionalities and less power consumption. This change, driven by the increasing demand of all sort of mobile devices and smart sensors, requires not only logic power and memory but also multi-standard wireless communication capabilities, sensing functionalities, and more important, longer battery life, thus low power operation. Systems-on-chip (SoC) are meant to integrate in a single chip not only the logic of one or several processors, but also graphical and power management units, power amplifiers, passive components, transceivers, and memory components. SoC with fully integrated multi-band multi-standard transceivers and RF front-ends are needed. HR-Si is currently used for the fabrication of RF circuits and HR-SOI substrates are now a mature and cost-effective technology for future SoCs. Unfortunately, their lossless RF capabilities are limited by the presence of a parasitic surface conduction. In addition, HR-Si and HR-SOI presents non-linear behaviour under large signal operation and the substrate electrical properties are frequency and voltage dependent. In this thesis, a CMOS compatible Si-based substrate for the integration of RF systems, named trap-rich HR-SOI, are investigated. The small-signal and large-signal performance of a series of Si, HR-Si, HR-SOI, trap-rich HR-Si, and (for the first time) commercial trap-rich HR-SOI wafers are characterized. The presence of trap-rich layer helps recovering the high-resistivity nominal and linear characteristics of HR-Si substrates. Moreover, compared to Si substrates, it also reduces the substrate crosstalk between adjacent devices. It is shown that the effective resistivity is a powerful figure-of-merit able to quantify the high-resistivity characteristics and nonlinear properties of HR-SOI and trap-rich HR-SOI substrates. Experimental measurements and physically-based simulations demonstrate that trap-rich HR-SOI substrates with effective resistivities higher than 3 kΩ-cm have excellent lossless and linear properties. Therefore, trap-rich HR-SOI wafers can be used for the integration of RF front-end in SoCs, with comparable performances to other more classical, and expensive, substrate solutions as SOS, SOQ or SOG.(FSA 3) -- UCL, 201

Nonlinear properties of Si-based substrates for wireless systems and SoC integration

The nonlinear behaviour of silicon substrates with different resistivities is analyzed using coplanar structures. In order to compare the nonlinear performance for different substrates and technologies, the harmonic distortion of crosstalk test structures is investigated, as well as the dependence on the distance. The generated harmonic components due to a large signal at 900 MH are measured using a one-tone network analyzer based setup. Below the crosstalk tap, harmonic levels as high as -43 and -54 dBc for 15 dBm are generated for standard and high-resistivity (HR) Si substrate, respectively. The introduction of a trap-rich layer at the interface between the BOX and the high-resistivity Si (HR-Si) provides a reduction of at least 45 dB in the harmonic distortion generated into the substrate. It has been proven that these results can be easily extrapolated to crosstalk structures with different dimensions

RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

In this paper, the nonlinear behavior of coplanar waveguide (CPW) transmission lines fabricated on Si and high-resistivity (HR) Si substrates is thoroughly investigated. Simulations and experimental characterization of 50- $Omega$ CPW lines are analyzed under small- and large-signal operation at 900 MHz for a wide variety of Si substrates with nominal resistivities from 10 $Omegahbox{-cm}$ up to values higher than 10 $hbox{k}Omegahbox{-cm}$. The introduction of a trap-rich layer to recover the Si substrate nominal HR characteristics is also considered. We experimentally demonstrate that the distortion level of a CPW line lying on Si substrate decreases with the effective resistivity sensed by the coplanar structure. Si substrates of effective resistivity higher than 3 $hbox{k}Omegahbox{-cm}$ present harmonic levels below $-$80 dBm for an output power of $+$15 dBm

Fabrication and Characterization of High Resistivity SOI Wafers for RF Applications

This paper provides an overview of the issues associated with parasitic surface conduction (PSC) in oxidized high resistivity (HR) Si wafers, such as HR SOI, in which PSC is related to the presence of free carriers at the substrate surface. Most of these issues are suppressed when the substrate surface is passivated with a trap-rich layer of material, such as polysilicon. A technique to fabricate substrate-passivated HR SOI wafer is presented, where the wafers are obtained by bonding a polysilicon-passivated HR Si substrate with an oxidized donor substrate. Preliminary encouraging bonding test results are presented

Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

Substrate crosstalk into standard and trap-rich high-resistivity silicon (HR-Si) substrates over a wide frequency range, from ultralow frequency (ULF) to extremely high-frequency band (EHF), is investigated using finite-element numerical simulations and experiments. It is demonstrated that low-frequency substrate crosstalk is strongly impacted by the presence of free carriers at the interface between the HR-Si substrate and the interconnection passivation layers. The efficiency of a trap-rich layer, a polysilicon layer thicker than 300 nm, placed at that interface to recover the nominal high-resistivity characteristic of the Si substrate is theoretically and experimentally demonstrated. Finally, the wideband crosstalk behavior of the HR-Si substrate with and without a trap-rich layer is modeled by means of a simple equivalent lumped-element circuit. The proposed model shows excellent agreement with finite-element numerical simulations and experimental data for frequencies above 100 kHz. Due to the introduction of a trap-rich layer, HR-Si substrate behaves as a lossless dielectric substrate. In that case, a purely capacitive electrical equivalent circuit is sufficient to properly describe the substrate crosstalk characteristics

RF performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate

RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications. © 1963-2012 IEEE