Optimizing CMOS circuits for low power using transistor reordering

This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. This power consumption depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by recording its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced.Peer ReviewedPostprint (published version

Individual flip-flops with gated clocks for low power datapaths

Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved.Peer ReviewedPostprint (published version

Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus

The energy at the I/O pins is a significant part of the overall consumption of a chip. To reduce this energy, this work extends to the data bus the working zone encoding method originally applied to encoding an external address bus. This method is based on the conjecture that programs favor a few working zones of their address space at each instant and that addresses to consecutive accesses for each zone frequently differ by a small amount. When the difference is small, instead of sending the whole address, the method sends an offset with respect to the previous address to that zone, together with an identifier for the zone. In this paper the same idea is extended to the data bus. The approach has been applied to several SPEC95 streams of references to memory along with the corresponding data values in a system with multiplexed address and multiplexed instruction/data buses. Moreover the effect of instruction and data caches is evaluated. Comparisons are given with previous methods for bus encoding, showing significant improvement in all cases except for the multiplexed address bus with instruction cache, where the best scheme depends on the overhead of the implementation.Peer ReviewedPostprint (published version

Scheduling and resource binding for low power

Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algorithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget.Peer Reviewe

High-level synthesis techniques for reducing the activity of functional units

Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during high-level synthesis (high-level transformations, scheduling and binding). Several techniques pursuing low power are proposed and the potential benefits evaluated. The common idea behind these techniques is to reduce the activity of the functional units (e.g. adders, multipliers) by minimizing the changes of their input operands. Preliminary evaluations obtained from switch-level simulations show that significant improvements can be achieved.Peer Reviewe

Working-zone encoding for reducing the energy in microprocessor address buses

The energy consumption due to input-output pins is a substantial part of the overall chip consumption. To reduce this energy, this work presents the working-zone encoding (WZE) method for encoding an external address bus, based on the conjecture that programs favor a few working zones of their address space at each instant. In such cases, the method identifies these zones and sends through the bus only the offset of this reference with respect to the previous reference to that zone, along with an identifier of the current working zone. This is combined with a one-hot encoding for the offset. Several improvements to this basic strategy are also described. The approach has been applied to several address streams, broken down into instruction-only, data-only, and instruction-data traces, to evaluate the effect on separate and shared address buses. Moreover, the effect of instruction and data caches is evaluated. For the case without caches, the proposed scheme is specially beneficial for data address and shared buses, which are the cases where other codings are less effective. On the other hand, for the case with caches the best scheme for the instruction-only and data-only traces is the WZE, whereas for the instruction-data traces it is either the WZE or the bus-invert with four groups (depending on the energy overhead of these techniques).Peer Reviewe

Exploiting the locality of memory references to reduce the address bus energy

The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. This method relies on the locality of memory references. Since applications favor a few working zones of their address space at each instant, for an address to one of these zones only the offset of this reference with respect to the previous reference to that zone needs to be sent over the bus, along with an identifier of the current working zone. This is combined with a modified one-shot encoding for the offset. An estimate of the area and energy overhead of the encoder/decoder are given; their effect is small. The approach has been applied to two memory-intensive examples, obtaining a bus-activity reduction of about 2/3 in both of them. Comparisons are given with previous methods for bus encoding, showing significant improvement.Peer ReviewedPostprint (author's final draft

Exploiting the locality of memory references to reduce the address bus energy

The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. This method relies on the locality of memory references. Since applications favor a few working zones of their address space at each instant, for an address to one of these zones only the offset of this reference with respect to the previous reference to that zone needs to be sent over the bus, along with an identifier of the current working zone. This is combined with a modified one-shot encoding for the offset. An estimate of the area and energy overhead of the encoder/decoder are given; their effect is small. The approach has been applied to two memory-intensive examples, obtaining a bus-activity reduction of about 2/3 in both of them. Comparisons are given with previous methods for bus encoding, showing significant improvement.Peer Reviewe

Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus

The energy at the I/O pins is a significant part of the overall consumption of a chip. To reduce this energy, this work extends to the data bus the working zone encoding method originally applied to encoding an external address bus. This method is based on the conjecture that programs favor a few working zones of their address space at each instant and that addresses to consecutive accesses for each zone frequently differ by a small amount. When the difference is small, instead of sending the whole address, the method sends an offset with respect to the previous address to that zone, together with an identifier for the zone. In this paper the same idea is extended to the data bus. The approach has been applied to several SPEC95 streams of references to memory along with the corresponding data values in a system with multiplexed address and multiplexed instruction/data buses. Moreover the effect of instruction and data caches is evaluated. Comparisons are given with previous methods for bus encoding, showing significant improvement in all cases except for the multiplexed address bus with instruction cache, where the best scheme depends on the overhead of the implementation.Peer Reviewe

Individual flip-flops with gated clocks for low power datapaths

Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved.Peer Reviewe