Structural, transport, optical and electronic properties of Sr2_2CoNbO6_6 thin films

We study the effect of substrate induced strain on the structural, transport, optical and electronic properties of Sr$_2$CoNbO$_6$ double perovskite thin films. The reciprocal space mapping, $\phi$-scan and high-resolution $\theta$-2$\theta$ scans of x-ray diffraction patterns suggest the epitaxial nature and high-quality of the films deposited on various single crystal ceramic substrates. A systematic enhancement in the dc electronic conductivity is observed with increase in the compressive strain, while a sharp reduction in case of tensile strain, which are further supported by change in the activation energy and density of states near the Fermi level. The optical band gap extracted from two distinct absorption bands, observed in the visible-near infrared spectroscopy show a non-monotonic behavior in case of compressive strain while significant enhancement with tensile strain. Unlike the bulk Sr$_2$CoNbO$_6$ (Co$^{3+}$ and Nb$^{5+}$), we observe different valence states of Co namely 2+, 3+ and 4+, and tetravalent Nb (4$d^1$) in the x-ray photoemission spectroscopy measurements. Moreover, a reduction in the average oxygen valency with the compressive strain due to enhancement in the covalent character of Co/Nb--O bond is evident. Interestingly, we observe sharp Raman active modes in these thin films, which indicates a significant enhancement in structural ordering as compared to the bulk.Comment: submitte

Ultra-low power circuits using graphene p-n junctions and adiabatic computing

Recent works have proven the functionality of electrostatically controlled graphene p–n junctions that can serve as basic primitive for the implementation of a new class of compact graphene-based reconfigurable multiplexer logic gates. Those gates, referred as RG-MUXes, while having higher expressive power and better performance w.r.t. standard CMOS gates, they also have the drawback of being intrinsically less power/energy efficient. In this work we address this problem from a circuit perspective, namely, we revisit RG-MUXes as devices that can operate adiabatically and hence with ultra-low (ideally, almost zero) power consumption. More specifically, we show how to build basic logic gates and, eventually, more complex logic functions, by appropriately interconnecting graphene-based p–n junctions as to implement the adiabatic charging principle. We provide a comparison in terms of power and performance against both adiabatic CMOS and their non-adiabatic graphene-based counterparts; characterization results collected from SPICE simulations on a set of representative functions show that the proposed ultra-low power graphene circuits can operate with 1.5–4 orders of magnitude less average power w.r.t. adiabatic CMOS and non-adiabatic graphene counterparts respectively. When it comes to performance, adiabatic graphene shows 1.3 (w.r.t. adiabatic CMOS) to 4.5 orders of magnitude (w.r.t. non-adiabatic technologies) better power-delay product

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

As an answer to the new electronics market demands, semiconductor industry is looking for different materials, new process technologies and alternative design solutions that can support Silicon replacement in the VLSI domain. The recent introduction of graphene, together with the option of electrostatically controlling its doping profile, has shown a possible way to implement fast and power efficient Reconfigurable Gates (RGs). Also, and this is the most important feature considered in this work, those graphene RGs show higher expressive power, i.e., they implement more complex functions, like Majority, MUX, XOR, with less area w.r.t. CMOS counterparts. Unfortunately, state-of-the-art synthesis tools, which have been customized for standard NAND/NOR CMOS gates, do not exploit the aforementioned feature of graphene RGs. In this paper, we present a post-synthesis tool that translates the gate level netlist obtained from commercial synthesis tools to a more optimized netlist that can efficiently integrate graphene RGs. Results conducted on a set of open-source benchmarks demonstrate that the proposed strategy improves, on average, both area and performance by 17% and 8.17% respectively

CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems

As an answer to More Moore paradigm, Complementary Metal Oxide Semiconductor (CMOS) technology is continuously scaled to nanometer lengths and the silicon channel has reached its physical limit. It is time for the industry to explore novel material based devices that support future integrated circuits. Graphene is a two dimensional material which can be patterned through existing lithography process, therefore representing the most interesting material for concurrent, single-layer integration of devices and interconnects. Moreover, it shows unique mechanical properties alowing for the growth of new smart devices (e.g. wearable computing). In this dissertation, we focus on a novel device called as multi function reconfigurable gate proposed by IBM. This device consists of coplanar split gates underneath a large graphene sheet. A thin dielectric oxide layer separates the gates and the graphene sheet. Three metal-graphene contacts are present on top of the graphene sheet, called as front metal-graphene contacts. The co-planar gates dope the graphene electrostatically by using bipolar voltages. Here, we define logic ‘0’ as negative voltage (-Vdd/2) and logic ‘1’ (+Vdd/2) as positive voltage. The gates are connected to ‘0’ and ‘1’ making the graphene region above the gates p-type and n-type, respectively. The device do not rely on patterning the graphene sheet into nanoribbons. Advanced CMOS lithography techniques can be efficiently used for the gate patterning to achieve high density integration. Thus, this device is feasible for manufacturing and does not introduce any edge effects on the carriers. Using the above mentioned multi function reconfigurable gate, with appropriate terminal connections, a graphene 2:1 multiplexer is realized. An equivalent electrical model (also verilog-A model) is developed which is integrated with commercial SPICE simulators. With appropriate signals at the data inputs of the graphene 2:1 multiplexer, several other basic boolean logic gates (Inv, AND, OR etc) are realized. Some of these gates (like AND etc) have multiple architectures and a thorough comparison in terms of power and performance is presented. For the graphene reconfigurable gate based logic gates, we identify the possible timing arcs. The timing arc is defined from the input node to the output node. Only those input node which is responsible for a signal transition at the output terminal are considered. Two classes of timing arcs are identified, one from back gate terminals to output terminal termed as back-to-out transition, second from front contact terminal to the output terminal termed as front-to-out transition. An analytical model for delay and power for each of these timing arcs are presented and validated through SPICE simulator. The model validation is done for a range of input transition time and output load capacitance. The next step is to build integrated circuits with these graphene based gates. This is termed as synthesis and is present in the initial stage of the traditional IC design flow. There are various synthesis methods for designing conventional CMOS based circuits. These methods (namely Standard Cell Mapping (STC), Binary Decision Diagrams (BDD) and Look Up Table (LUT)) can be adopted for graphene RG based gates too. Various benchmark circuits implemented with these methods are characterized for power, area and performance. This helps designers in identifying the best implementation style for low power and high performance circuit. From testability perspective, the effect of various physical defects such as Short circuit between device terminals and open terminals on the graphene RG based logic gates is presented in this thesis. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, have been analyzed and mapped at a higher level of abstraction using proper fault models. Finally, in this thesis we propose ultra low power graphene logic gates, based on Adiabatic Computing. We design graphene pn-junction based adiabatic logic gates (INV/AND/OR) and are characterized for power and performance. A comparison between the graphene pn-junction based adiabatic logic gates and non adiabatic graphene logic gates is drawn and the adiabatic gates proved to have significant power savings

Use of Mycobacterium smegmatis Deficient in ADP-Ribosyltransferase as Surrogate for Mycobacterium tuberculosis in Drug Testing and Mutation Analysis

Rifampicin (Rif) is a first line drug used for tuberculosis treatment. However, the emergence of drug resistant strains has necessitated synthesis and testing of newer analogs of Rif. Mycobacterium smegmatis is often used as a surrogate for M. tuberculosis. However, the presence of an ADP ribosyltransferase (Arr) in M. smegmatis inactivates Rif, rendering it impractical for screening of Rif analogs or other compounds when used in conjunction with them (Rif/Rif analogs). Rifampicin is also used in studying the role of various DNA repair enzymes by analyzing mutations in RpoB (a subunit of RNA polymerase) causing Rif resistance. These analyses use high concentrations of Rif when M. smegmatis is used as model. Here, we have generated M. smegmatis strains by deleting arr (Delta arr). The M. smegmatis Delta arr strains show minimum inhibitory concentration (MIC) for Rif which is similar to that for M. tuberculosis. The MICs for isoniazid, pyrazinamide, ethambutol, ciprofloxacin and streptomycin were essentially unaltered for M. smegmatis Delta arr. The growth profiles and mutation spectrum of Delta arr and, Delta arr combined with Delta udgB (udgB encodes a DNA repair enzyme that excises uracil) strains were similar to their counterparts wild-type for arr. However, the mutation spectrum of Delta fpg Delta arr strain differed somewhat from that of the Delta fpg strain (fpg encodes a DNA repair enzyme that excises 8-oxo-G). Our studies suggest M. smegmatis Delta arr strain as an ideal model system in drug testing and mutation spectrum determination in DNA repair studies

Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process

International audienceSingle Event Effects introduce soft errors in ASICs. Design methodologies like Triple ModularRedundancy (TMR) with clock skew insertion, a system level redundancy technique is a commonpractice by designers to mitigate soft errors. However, the optimal spacing between memoryelements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASICdevelopment under the framework of the CERN RD53 collaboration to characterize the soft errorrates against the separation spacing and clock skew between memory elements in a TMR. Thisarticle describes the architecture and design aspects of the various test structures on the RD53SEUtest chip

Competitive exclusion of uropathogenic <i>E. coli</i> biofilm by <i>Salmonella</i> through matrix inhibition

SummaryBiofilm is a predominant lifestyle of bacteria in host and non-host environments with cell collectives and extracellular matrix as the defining principles of biofilm. Several factors trigger biofilm formation including response to competition. Urinary tract infections (UTI) are highly prevalent worldwide and mainly caused by uropathogenic E. coli (UPEC), which progresses into chronic form due to the biofilm formation by the pathogen. In this study, we hypothesized that competition for territorial space could occur between species by intervening in the biofilm matrix production, particularly of UPEC, thereby reducing its colonizing ability. UPEC colony displays different morphology in congo red media based on matrix production, which we exploited for screening bacterial isolates capable of inhibiting the matrix. This was validated by using the cell-free supernatants of the isolates to impair UPEC biofilm. Isolates that inhibited matrix production belonged to species of Shigella, Escherichia, Enterobacter, and Salmonella from Enterobacteriaceae family. Competition experiments between the isolates and UPEC revealed spiteful interactions particularly during biofilm formation, indicating fierce competition for territorial space colonization. The isolate Salmonella enterica B1 could competitively exclude UPEC in the biofilm. Altogether, we show that interference competition by matrix inhibition occurs as a strategy by bacteria to colonize territorial space.</jats:p