33 research outputs found

    A Distributed Electrical Model for Interdigitated back Contact Silicon Solar Cells

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    AbstractIn this paper we introduce a quasi 3-D electrical model for a high efficiency interdigitated back contact (IBC) solar cell. This distributed electrical network is based on two-diodes circuit elementary units. It allows accounting for the resistive losses due to the transport through the emitter, the back surface field (BSF) and the fingers and busbars metallization. Moreover, it can model the electrical shading losses attributed to the BSF busbar. We calibrated the electrical components of the model according to experimental measurements on real devices. The validity of the model is demonstrated by the good agreement between simulation and experimental results for dark and illuminated IV measurements with and without masked busbars. The model can now easily be applied to simulate and optimize different metal grid layouts

    Process Development of Silicon Heterojunction Interdigitated Back-Contacted (SHJ-IBC) Solar Cells Bonded to Glass

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    In imecÔÇÖs i2-module concept, silicon heterojunction interdigitated back-contacted (SHJ-IBC) solar cells are fabricated on monocrystalline foils bonded to glass. The proposed technology allows for cell processing on thin wafers mechanically supported by the glass, increasing the yield of processing such thin wafers. A process sequence for SHJ-IBC cell fabrication that can be applied to bonded thin foils is described. We investigated and optimized individual process steps on thick wafers. Then the developed steps were integrated into a process flow to fabricate solar cells on wafers with different thicknesses and bonding agents. On wafers with a thickness of 190 ╬╝m, functional cells with efficiencies of 22.6% and 21.7% were made on freestanding and silicone bonded wafers, respectively. On thin wafers of 57 ╬╝m, our best SHJ-IBC cell on an EVA bonded wafer exhibits excellent Voc of 740 mV and efficiency of 20.0%, which demonstrates the high potential of the i2-module concept

    Charge Trapping in Organic Field-Effect Transistors and Applications for Photodetectors and Memory Devices (Ladingsvangst in organische veld-effect transistoren en toepassingen in fotodetectoren en geheugenelementen)

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    Kristallijn silicium (Si) is sinds meerdere decennia de dominerende tech nologie in de halfgeleider industrie. Voor bepaalde toepassingen zijn du nne film technologie├źn nochtans beter geschikt. In kristallijn Si techno logie vertrekken alle productiestappen van de kristallijne wafer. Deze w afer is breekbaar en heeft een beperkte oppervlakte. In dunne film techn ologie├źn daarentegen, wordt de halfgeleider als een film op een willekeu rig substraat met een willekeurige grootte gedeponeerd. In bepaalde geva llen kan het substraat zelfs flexibel zijn. Hierdoor behoren beeldscherm en met grote oppervlaktes, zonnecellen met de afmetingen van een volledi ge vensterruit en opvouwbare scanners tot de haalbare toepassingen. Orga nische halfgeleiders zijn een mogelijke dunne film technologie. De stabiliteit van de halfgeleider component tijdens gebruik is essentie el om een betrouwbare toepassing met een lange levensduur te realiseren. Een onstabiele veld-effect transistor kan gekarakteriseerd worden door een verschuiving van de transfer curves. Externe factoren zoals the aang elegde spanningen aan de contacten, belichting, of het zuurstof en water gehalte in de lucht kunnen deze verschuiving be├»nvloeden. Hoewel deze v erschuivingen meestal niet gewenst zijn, kunnen ze in bepaalde gevallen toch nuttig zijn. Een kleine verschuiving van de transfer curves leidt n amelijk tot een grote verandering in stroom bij een vaste uitleesspannin g. Op deze manier kan de transistor gebruikt worden als een gevoelige se nsor voor de eerder vermelde externe factoren. Als de transfer curves oo k nog stabiel blijken te zijn op hun nieuwe posities na de verschuiving, kan de component zelfs gebruikt worden als een geheugenelement. E├ęn van de mechanismes die een verschuiving van de transfer curve kunnen veroorzaken is het vangen van ladingsdragers. Deze ladingsdragers zijn eerst mobiel in de halfgeleider en worden dan gevangen in vangstcentra i n de halfgeleider, aan het tussenoppervlak tussen halfgeleider en gate i solator, of in de gate isolator zelf. Eerst wordt het vangen van ladingsdragers aan het tussenoppervlak tussen halfgeleider en gate isolator bestudeerd. We tonen aan dat belichting h et vangen van ladingsdragers versnelt, maar dat het effect te traag is o m eenvoudige transistors als licht detector te gebruiken. Dit laatste is in tegenstelling met wat er in de literatuur wordt beweerd. Bovendien b ewijzen we dat de verschuiving van de transfer curves onder belichting z ich gelijkaardig gedraagt als de verschuiving in het donker onder de inv loed van aangelegde spanningen aan de contacten. Het effect van belichti ng is het aanvoeren van extra, photogegenereerde ladingsdragers die kunn en gevangen worden. Deze vaststelling leidt tot een beter begrip van de instabiliteitsmechanismes in organische transistors. Het gebruik van org anische transistors als licht detector wordt door deze vaststelling ook verder gehypothekeerd, aangezien een gevoelige sensor onvermijdelijk ook instabiel zal zijn tijdens de uitlezing. Vervolgens wordt het vangen van ladingsdragers in de gate isolator bestu deerd. We tonen aan dat ladingen kunnen opgeslagen worden in een gate is olator bestaande uit een oxide en een polymere isolator. Korte programma tiepulsen van 1,5 ms met een programmatiespanning van ┬▒15 V zijn ge noeg om ladingsdragers op te slaan en vervolgens te verwijderen uit de g ate isolator. De retentie van de ladingsdragers bedraagt meer dan drie m aanden, wat langer is dan elke component met ladingsdragersvangst die to t nu toe is beschreven in de literatuur. Bovendien worden meer dan 500 s chrijf- en wiscycli gedemonstreerd. Deze vaststellingen tonen aan dat de ze component kan gebruikt worden als een herprogrammeerbaar geheugenelem ent met twee stabiele geheugentoestanden. Daarna wordt het vangen van gaten en elektronen in de gate isolator verd er vergeleken en wordt aangetoond dat beiden noodzakelijk zijn om de com ponent te kunnen herprogrammeren bij lage spanningen. Tenslotte worden t wee meer complexe structuren voorgesteld, nog steeds met aan gate isolat or bestaande uit een oxide en een polymeer. Deze structuren kunnen gemak kelijk ge├»ntegreerd worden met het circuit voor de adressering en het ui tlezen van het geheugenelement. Op deze manier zou een complete geheugen matrix in organische halfgeleider technologie kunnen gerealiseerd worden .Dankwoord Samenvatting Summary List of symbols and abbreviations Contents 1 Organic field-effect transistors 1.1 Thin-film transistors 1.2 Organic semiconducting materials 1.2.1 From carbon atom to semiconducting film 1.2.2 Short lexicon of typical terms and issues 1.3 Basic structure and operation 1.4 Materials and device fabrication 1.4.1 Organic semiconductor 1.4.2 Gate dielectric 1.4.3 Source and drain electrodes 1.4.4 Patterning 1.5 Device characterization 1.5.1 Standard transistor measurements 1.5.2 Measurements under illumination 1.5.3 Temperature dependent measurements 1.6 Objectives and outline of the manuscript 2 Shifts of the transfer curve 2.1 The onset voltage, the flat band voltage and the threshold voltage 2.1.1 The onset voltage 2.1.2 The onset voltage versus the flat band voltage 2.1.3 The onset voltage versus the threshold voltage 2.1.4 Tracking shifts of the transfer curves 2.2 Hysteresis 2.2.1 Polarization of the gate dielectric 2.2.2 Trapping of charges coming from the semiconductor 2.2.3 Trapping of charges coming from the gate 2.3 Bias stress 2.3.1 Bias stress in a-Si field-effect transistors 2.3.2 Bias stress in OTFTs 2.4 Stability under environmental conditions 2.5 Ferroelectric memory transistors 3 A charge trapping phototransistor 3.1 Illumination of organic field-effect transistors 3.1.1 Photoconductive and photovoltaic effect 3.1.2 Trapping sites for the electrons 3.1.3 Figures of merit for a photodetector 3.1.4 Corrections and comments to the literature 3.2 Experimental 3.2.1 Device structure 3.2.2 Measurement method 3.3 Results and discussion 3.3.1 Negative versus positive gate-source bias 3.3.2 Different treatments of the interface 3.3.3 Illumination at different wavelengths 3.4 Conclusions and outlook 3.4.1 Conclusions regarding bias stress 3.4.2 Conclusions regarding the use of organic photoFETs 4 A charge trapping memory transistor 4.1 Charge trapping memory transistors 4.1.1 Si charge trapping memory transistors 4.1.2 Organic charge trapping memory transistors 4.2 Experimental 4.2.1 Device structure 4.2.2 Measurement method 4.3 Results and discussion 4.3.1 Charge trapping as a function of programming voltage 4.3.2 Charge trapping as a function of programming time 4.3.3 Retention 4.3.4 Endurance 4.4 Conclusions 5 Electrons and holes in a charge trapping memory transistor 5.1 Experimental 5.1.1 Device structure 5.1.2 Measurement method 5.2 Results and discussion 5.2.1 An ambipolar device 5.2.2 No electron accumulation 5.2.3 No hole accumulation 5.2.4 Field distribution during write and erase 5.2.5 Temperature dependent supply of charge carriers 5.2.6 Supply of charge carriers by illumination 5.3 Conclusions 6 Towards integration 6.1 Experimental 6.1.1 Device structure 6.1.2 Measurement method 6.2 Results on the intermediate structure 6.2.1 Charge trapping as a function of programming voltage 6.2.2 Endurance 6.2.3 Retention 6.3 Results on the final structure 6.3.1 Charge trapping as a function of programming voltage 6.3.2 Endurance 6.3.3 Retention 6.4 Conclusions and further outlook 7 General conclusions and future outlook Bibliography Curriculum vitae List of publicationsnrpages: 137status: publishe

    Charge trapping in organic transistor memories: On the role of electrons and holes

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    In this work, we study charge trapping in organic transistor memories with a polymeric insulator as gate dielectric. We found that the mechanism of charge trapping is tunneling from the semiconductor channel into the gate dielectric. Depending on the semiconductor and its processing, charge trapping can result in large bi-directional threshold voltage shifts, in case the semiconductor is ambipolar, or in shifts in only one direction (unipolar semiconductor). These results indicate that optimal memory performance requires charge carriers of both polarities, because the most efficient method to lower the programming field is by overwriting a trapped charge by an injected charge of opposite polarity. (C) 2009 Elsevier B.V. All rights reserved.status: publishe

    Understanding the Influence of Busbars in Large-Area IBC Solar Cells by Distributed SPICE Simulations

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    none5In this paper, we model a large-area high-efficiency interdigitated back-contact (IBC) solar cell by means of a distributed electrical network. The simulation tool allows accounting for the distributed resistive effects in diffusions and metallization. The model also considers the electrical shading effect and resistive losses due to both back-surface field (BSF) and emitter busbars. A calibrated model is used to investigate the case of a large-area (15.6 ├Ś 15.6 cm2) IBC cell, in which we investigate the influence of key busbar parameters: number of busbars, busbar width, soldering pitch (for module connection), and metal sheet resistance. The predictive simulations allow finding out the optimum number of busbars, arising from a tradeoff between the electrical shading effect due to the BSF busbars and resistive losses due to the emitter busbars and the fingers. Moreover, we show how the distance between soldering points on the metal busbars influences the choice of the busbar width. We found out that if an adequate number (>7) of soldering points is adopted, the busbar width should be kept lower than 0.5 mm. On the other hand, the adoption of a thick Cu-plating (15 ╬╝m) leads to an increase of efficiency of 0.2%abs with respect to the case of sputtered Al metal (3 ╬╝m thick).nonePaolo Magnone;Maarten Debucquoy;Daniele Giaffreda;Niels Posthuma;Claudio FiegnaMagnone, Paolo; Maarten, Debucquoy; Daniele, Giaffreda; Niels, Posthuma; Claudio, Fiegn

    Understanding the Influence of Busbars in Large-Area IBC Solar Cells by Distributed SPICE Simulations

    No full text
    In this paper we model a large-area high-efficiency interdigitated back-contact (IBC) solar cell by means of a distributed electrical network. The simulation tool allows accounting for the distributed resistive effects in diffusions and metallization. The model also considers the electrical shading effect and resistive losses due to both BSF and emitter busbars. A calibrated model is used to investigate the case of a large-area (15.6x15.6 cm2) IBC cell, in which we investigate the influence of key busbar parameters: number of busbars; busbar width; soldering pitch (for module connection); metal sheet resistance. The predictive simulations allow finding out the optimum number of busbars, arising from a tradeoff between the electrical shading effect due to the BSF busbars and resistive losses due to the emitter busbars and the fingers. Moreover, we show how the distance between soldering points on the metal busbars, influences the choice of the busbar width. We found out that, if an adequate number (>7) of soldering points is adopted, the busbar width should be kept lower than 0.5mm. On the other hand, the adoption of a thick Cu-plating (15╬╝m) leads to an increase of efficiency of 0.2%abs with respect to the case of sputtered Al metal (3╬╝m thick)

    An organic charge trapping memory transistor with bottom source and drain contacts

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    We present an organic charge trapping memory transistor with lithographically defined bottom source and drain contacts. This device can be written and erased at voltages as low as 15 V. More than 500 write and erase cycles and the retention of the trapped charge over more than three months are shown, demonstrating the possibilities of this device as a reprogramable nonvolatile organic memory element.status: publishe

    Four-Terminal Perovskite/Silicon Multijunction Solar Modules

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    Contains fulltext : 187499.pdf (publisher's version ) (Closed access)8 p

    Charge trapping in organic transistor memories:On the role of electrons and holes

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    \u3cp\u3eIn this work, we study charge trapping in organic transistor memories with a polymeric insulator as gate dielectric. We found that the mechanism of charge trapping is tunneling from the semiconductor channel into the gate dielectric. Depending on the semiconductor and its processing, charge trapping can result in large bi-directional threshold voltage shifts, in case the semiconductor is ambipolar, or in shifts in only one direction (unipolar semiconductor). These results indicate that optimal memory performance requires charge carriers of both polarities, because the most efficient method to lower the programming field is by overwriting a trapped charge by an injected charge of opposite polarity.\u3c/p\u3

    Correlation between bias stress instability and phototransistor operation of pentacene thin-film transistors

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    The authors study the use of pentacene thin-film transistors as phototransistors. The shift in turn-on voltage (V-on), responsible for the high photosensitivity of these devices, is shown to be strongly dependent on illumination time and applied gate voltage. The time dependence of this process is similar to the shift in V-on during bias stress experiments in the dark, and illumination can simply be accounted for as an acceleration factor for bias stress instability. By comparing the characteristics of devices with different gate dielectrics, trapping of electrons by OH groups at the gate dielectric interface is indicated as a main origin for these shifts. (C) 2007 American Institute of Physics.status: publishe
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