D-Band Beamforming ×8 Multiplier Chain in 28-nm FD-SOI CMOS

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Free-Space Permittivity Measurement for Inhomogeneous PSV-Coated Si-wafer at Frequencies from 75 GHz to 325 GHz

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E-band CMOS Built-in Self-Test Circuit Capable of Testing Active Antenna Impedance and Complex Channel Response

1

E-band CMOS Built-in Self-Test Circuit Capable of Testing Active Antenna Impedance and Complex Channel Response

1

220 - 265 GHz Active ×6 Frequency Multiplier MMIC with InP HEMT Technology

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A Broadband D-Band Dual-Peak Gmax -Core Amplifier With a T-Shaped Embedding Network in CMOS

11Nsciescopu

13-K Tnoise Cryo-CMOS Parametric Amplifier at 80 mK for Quantum Computers

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13-K T_noise Cryo-CMOS Parametric Amplifier at 80 mK for Quantum Computers

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Analysis and Design of Multi-Stacked FET Power Amplifier With Phase-Compensation Inductors in Millimeter-Wave Band

Stacked-FET topology is analyzed to increase the output power of a power amplifier (PA) in the millimeter-wave (mm-wave) band. In the mm-wave band, parasitic capacitances of the transistor severely degrade stacking efficiency due to the phase mismatch between stacked FETs. The phase-compensation (PC) inductances, including the losses of the inductor for the best stacking efficiency, are presented in both series and shunt connections. From this analysis, a triple-stacked-FET PA is designed in the F -band. Proper PC series or shunt inductor types are used between the first and second stacked FETs and between the second and third stacked FETs in consideration of the core layout and inductor size. The PA is fabricated in the 28-nm CMOS fully depleted silicon-on-insulator (FD-SOI) process. With a compact core area of 0.054 mm 2 , the PA achieves peak PSAT and PAE MAX of 15.1 dBm and 18.6%, respectively.11Nsciescopu