379 research outputs found
Dependable reconfigurable multi-sensor poles for security
Wireless sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical [1]. An example of a multi-sensor pole is shown. Crucial attribute in these systems for security, especially in harsh environment, is a high robustness and guaranteed availability during lifetime. This environment could include molest. In this paper, two approaches are used which are applied simultaneously but are developed in different projects. \u
Testing microelectronic biofluidic systems
According to the 2005 International Technology Roadmap for Semiconductors, the integration of emerging nondigital CMOS technologies will require radically different test methods, posing a major challenge for designers and test engineers. One such technology is microelectronic fluidic (MEF) arrays, which have rapidly gained importance in many biological, pharmaceutical, and industrial applications. The advantages of these systems, such as operation speed, use of very small amounts of liquid, on-board droplet detection, signal conditioning, and vast digital signal processing, make them very promising. However, testable design of these devices in a mass-production environment is still in its infancy, hampering their low-cost introduction to the market. This article describes analog and digital MEF design and testing method
Test-Signal Search for Mixed-Signal Cores in a System-on-Chip
The well-known approach towards testing mixed-signal cores is functional testing and basically measuring key parameters of the core. However, especially if performance requirements increase, and embedded cores are considered, functional testing becomes technically and economically less attractive. A more cost-effective approach could be accomplished by a combination of reduced functional tests and added structural tests. In addition, it will also improve the debugging facilities of cores. Basic problem remains the large computational effort for analogue structural testing. In this paper, we introduce the concept of Testability Transfer Function for both analogue as well as digital parts in a mixed-signal core. This opens new possibilities for efficient structural testing of embedded mixed-signal cores, thereby adding to\ud
the quality of tests
Improved method for SNR prediction in machine-learning-based test
This paper applies an improved method for testing the signal-to-noise ratio (SNR) of Analogue-to-Digital Converters (ADC). In previous work, a noisy and nonlinear pulse signal is exploited as the input stimulus to obtain the signature results of ADC. By applying a machine-learning-based approach, the dynamic parameters can be predicted by using the signature results. However, it can only estimate the SNR accurately within a certain range. In order to overcome this limitation, an improved method based on work is applied in this work. It is validated on the Labview model of a 12-bit 80 Ms/s pipelined ADC with a pulse- wave input signal of 3 LSB noise and 7-bit nonlinear rising and falling edges
Dependable Digitally-Assisted Mixed-Signal IPs Based on Integrated Self-Test & Self-Calibration
Heterogeneous SoC devices, including sensors, analogue and mixed-signal front-end circuits and the availability of massive digital processing capability, are being increasingly used in safety-critical applications like in the automotive, medical, and the security arena. Already a significant amount of attention has been paid in literature with respect to the dependability of the digital parts in heterogeneous SoCs. This is in contrast to especially the sensors and front-end mixed-signal electronics; these are however particular sensitive to external influences over time and hence determining their dependability. This paper provides an integrated SoC/IP approach to enhance the dependability. It will give an example of a digitally-assisted mixed-signal front-end IP which is being evaluated under its mission profile of an automotive tyre pressure monitoring system. It will be shown how internal monitoring and digitally-controlled adaptation by using embedded processors can help in terms of improving the dependability of this mixed-signal part under harsh conditions for a long time
Two improved methods for testing ADC parametric faults by digital input signals
In this paper, two improved methods are presented extending our previous work. The first one improves the results by adjusting the voltage levels of the input pulse wave stimulus. Compared with the sine wave input stimulus, the four-level pulse wave can detect even more faulty cases with the offset faults. The second one improves the results by calculating the similarity of the output spectra between the golden devices and the DUTs. Compared with the previous method [10], it is less sensitive to the jitter and the change of the rise/fall time of the input pulse wave stimulus. In these two methods, a number of golden devices are tested at first to obtain the fault-free range. At last, a signature result is obtained from both methods. It can filter out the faulty devices in a quick way before testing the specific values of the conventional dynamic and static parameters
The test ability of an adaptive pulse wave for ADC testing
In the conventional ADC production test method, a high-quality analogue sine wave is applied to the Analogue-to-Digital Converter (ADC), which is expensive to generate. Nowadays, an increasing number of ADCs are integrated into a system-on-chip (SoC) platform design, which usually contains a digital embedded processor. In such a platform, a digital pulse wave is obviously less expensive to generate than an accurate analogue sine wave. As a result, the usage of a digital pulse wave has been investigated to test ADCs as the test stimulus. In this paper, the ability of a digital adaptive pulse wave for ADC testing is presented via the measurement results. Instead of the conventional FFT analysis, a time-domain analysis is exploited for post-processing, from which a signature result can be obtained. This signature can distinguish between faulty devices and the fault-free devices. It is also used in the machine-learning-based test method to predict the dynamic specifications of the ADC. The experimental results of a 12-bit 80 M/s pipelined ADC are shown to evaluate the sensitivity and accuracy of using a pulse wave to test an ADC
Towards Structural Testing of Superconductor Electronics
Many of the semiconductor technologies are already\ud
facing limitations while new-generation data and\ud
telecommunication systems are implemented. Although in\ud
its infancy, superconductor electronics (SCE) is capable of\ud
handling some of these high-end tasks. We have started a\ud
defect-oriented test methodology for SCE, so that reliable\ud
systems can be implemented in this technology. In this\ud
paper, the details of the study on the Rapid Single-Flux\ud
Quantum (RSFQ) process are presented. We present\ud
common defects in the SCE processes and corresponding\ud
test methodologies to detect them. The (measurement)\ud
results prove that we are able to detect possible random\ud
defects for statistical purposes in yield analysis. This\ud
paper also presents possible test methodologies for RSFQ\ud
circuits based on defect oriented testing (DOT)
redicting dynamic specifications of ADCs with a low-quality digital input signal
A new method is presented to test dynamic parameters of Analogue-to-Digital Converters (ADC). A noisy and nonlinear pulse is applied as the test stimulus, which is suitable for a multi-site test environment. The dynamic parameters are predicted using a machine-learning-based approach. A training step is required in order to build the mapping function using alternate signatures and the conventional test parameters, all measured on a set of converters. As a result, for industrial testing, only a simple signature-based test is performed on the Devices-Under-Test (DUTs). The signature measurements are provided to the mapping function that is used to predict the conventional dynamic parameters. The method is validated by simulation on a 12-bit 80 Ms/s pipelined ADC with a pulse wave input signal of 3 LSB noise and 7-bit nonlinear rising and falling edges. The final results show that the estimated mean error is less than 4% of the full range of the dynamic specifications
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