21,383 research outputs found

    Attainable lengths for circular binary words avoiding k-powers

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    We show that binary circular words of length n avoiding 7/3+ powers exist for every sufficiently large n. This is not the case for binary circular words avoiding k+ powers with k < 7/3https://projecteuclid.org/download/pdf_1/euclid.bbms/113379334

    Analysis and equalization of data-dependent jitter

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    Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

    The Number of Ternary Words Avoiding Abelian Cubes Grows Exponentially

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    We show that the number of ternary words of length n avoiding abelian cubes grows faster than r^n, where r = 2^{1/24}NSERCcs.uwaterloo.ca/journals/JIS/VOL7/Currie/currie18.pd

    A 10Gb/s data-dependent jitter equalizer

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    An equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB

    Towards In-Transit Analytics for Industry 4.0

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    Industry 4.0, or Digital Manufacturing, is a vision of inter-connected services to facilitate innovation in the manufacturing sector. A fundamental requirement of innovation is the ability to be able to visualise manufacturing data, in order to discover new insight for increased competitive advantage. This article describes the enabling technologies that facilitate In-Transit Analytics, which is a necessary precursor for Industrial Internet of Things (IIoT) visualisation.Comment: 8 pages, 10th IEEE International Conference on Internet of Things (iThings-2017), Exeter, UK, 201
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