126 research outputs found

    The Role of the Substrate on Pattern-Dependent Charging

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    Monte Carlo simulations of charging and profile evolution during plasma etching reveal that the substrate can mediate current imbalance across the wafer. This function couples patterned areas, where the electron shading effect dominates, to substrate areas directly exposed to the plasma. When a net positive current flows through the pattern features to the substrate, increasing the exposed area decreases the substrate potential, thereby causing notching at the connected feature sidewalls to worsen, in agreement with experimental observations

    Prediction of multiple-feature effects in plasma etching

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    Charging and topography evolution simulations during plasma etching of dense line-and-space patterns reveal that multiple-feature effects influence critically the etch profile characteristics of the various lines. By including neighboring lines, the simulation predicts a peculiar notching behavior, where the extent of notching varies with the location of the line. Feature-scale modeling can no longer be focused on individual features alone; "adjacency" effects are crucial for understanding and predicting the outcome of etching experiments at reduced device dimensions

    Simulation of current transients through ultrathin gate oxides during plasma etching

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    Monte Carlo simulations of electron tunneling through a 3 nm gate oxide during etching of dense patterns of gate electrodes in uniform high-density plasmas reveal two current transients, which occur: (a) when the open area clears, and (b) when the polysilicon lines just become disconnected at the bottom of trenches. The first charging transient is fast (controlled by charging) and may be followed by a steady-state current which lasts until the lines get disconnected. The second charging transient lasts longer; the magnitude of the tunneling current generally decreases as the sloped polysilicon sidewalls become straighter. Most of the damage occurs at the edge gate when the open areas are covered by field oxide; however, the edge gate suffers no damage when the 3 nm oxide extends into the open areas

    The influence of electron temperature on pattern-dependent charging during etching in high-density plasmas

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    The effect of the electron temperature (Te) on charging potentials that develop in trenches during plasma etching of high aspect ratio polysilicon-on-insulator structures is studied by two-dimensional Monte Carlo simulations. Larger values of Te cause the potential of the upper photoresist sidewalls to become more negative; thus, more electrons are repelled back and the electron current density to the trench bottom decreases. The ensuing larger charging potential at the bottom surface perturbs the local ion dynamics so that more ions are deflected towards the polysilicon sidewalls causing (a) more severe lateral etching (notching) and (b) larger gate potentials, thereby increasing the probability of tunneling currents through the underlying gate oxide. The simulation results capture reported experimental trends and offer new insight into the nature of charging damage

    On the link between electron shadowing and charging damage

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    Charging and topography evolution simulations during plasma etching of high aspect ratio line-and-space patterns reveal that electron shadowing of the sidewalls critically affects charging damage. Decreasing the degree of electron shadowing by using thinner masks decreases the potentials of the etched features with a concomitant reduction in Fowler–Nordheim tunneling currents through underlying thin gate oxides. Simultaneously, the potential distribution in the trench changes, significantly perturbing the local ion dynamics which, in turn, cause the notching effect to worsen. Since the latter can be reduced independently by selecting an appropriate etch chemistry, the use of thinner (hard) masks is predicted to be advantageous for the prevention of gate oxide failure

    Role of film conformality in charging damage during plasma-assisted interlevel dielectric deposition

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    While observations of charging damage during plasma-assisted deposition have been erratic thus far, concern abounds that it may worsen as aspect ratios increase and high-density plasmas are used more frequently. Simulations of pattern-dependent charging during interlevel dielectric deposition reveal that the initial conformality of the dielectric film plays a crucial role in metal line charge up and the subsequent degradation to the buried gate oxide, to which the metal line is connected. For moderate aspect ratios, significant charging damage occurs for nonconformal step coverage

    Electron irradiance of conductive sidewalls: A determining factor for pattern-dependent charging

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    Numerical simulations of charging and profile evolution during gate electrode overetching in high density plasmas have been performed to investigate the effect of long conductive sidewalls on profile distortion (notching). The results reveal that the angle of electron irradiance of the conductive portion of the sidewalls affects profoundly the charging potential of the gates. Larger angles, obtained for thinner masks and/or thicker polysilicon, result in reduced gate potentials which, through their influence on the local ion dynamics, cause more severe notching at all lines of the microstructure

    Pattern-Dependent Charging in Plasmas: Electron Temperature Effects

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    The differential charging of high-aspect-ratio dense structures during plasma etching is studied by two-dimensional Monte Carlo simulations. Enhanced electron shadowing at large electron temperatures is found to reduce the electron current density to the bottom of narrow trenches, causing buildup of large charging potentials on dielectric surfaces. These potentials alter the local ion dynamics, increase the flux of deflected ions towards the sidewalls, and result in distorted profiles. The simulation results capture reported experimental trends and reveal the physics of charging damage

    The influence of mask thickness on charging damage during overetching

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    Feature-scale charging simulations during gate electrode overetching in high-density plasmas reveal that the thickness of the insulating mask plays a critical role in charging damage. When thinner masks are used, the electron irradiance of the conductive part of the sidewalls increases, causing the charging potentials of the polysilicon lines to decrease, thus reducing the probability for catastrophic tunneling currents through the underlying oxide. Simultaneously, changes in the charging potential distribution at the bottom SiO2 surface cause a significant perturbation in the local ion dynamics which, in turn, adversely affects notching. Notches are predicted to form everywhere in a line-and-space structure, even when the lines are electrically isolated. The results suggest that the trend toward thinner (hard) masks—to keep the aspect ratio low as device dimensions shrink—should reduce oxide failure but at the cost of more severe notching
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