Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm Al2O3, SiO2 equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage (Vth) instability under negative gate bias stress at various measurement delays (tm), stress biases (VGSTR), temperatures (T), and stress times (tstr) for the first time. Thin top-gated oxide enables low VGSTR that is closer to the operating condition and ultrafast Vth measurements with low delay (tm = 10 μs, due to high drain current) that ensure minimal recovery. The resultant time kinetics of Vth degradation (ΔVth) shows fast saturation at longer stress times and low-temperature activation energy. Vth instability in these top-gated devices is suggested to be dominated by hole trapping, which is modeled using first-order equations at different VGSTR and T. It is shown that measurements using larger tm show lower degradation magnitude that do not saturate due to recovery artifacts and give inaccurate estimation of hole trap densities. Conventional, thick, and global back-gated oxide BP-FETs were also fabricated and characterized for varying tm (1 ms being the lowest due to a low drain current level for thick oxide), VGSTR, and T to benchmark our top-gated results. Nonsaturating ΔVth in the back-gated devices is shown to result from recovery artifacts due to the large tm (1 ms and greater) values. Finally, using a VGSTR and T-dependent first-order model, we show that the top-gated Al2O3 BP-FETs with scaled gate oxide thickness can match state-of-the-art Si reliability specifications at operating voltage and room/elevated temperature

Polarity-Tunable Photocurrent through Band Alignment Engineering in a High-Speed WSe₂/SnSe₂ Diode with Large Negative Responsivity

Excellent light–matter interaction and a wide range of thickness-tunable bandgaps in layered vdW materials coupled by the facile fabrication of heterostructures have enabled several avenues for optoelectronic applications. Realization of high photoresponsivity at fast switching speeds is a critical challenge for 2D optoelectronics to enable high-performance photodetection for optical communication. Moving away from conventional type-II heterostructure pn junctions towards a WSe2/SnSe2 type-III configuration, we leverage the steep change in tunneling current along with a light-induced heterointerface band shift to achieve high negative photoresponsivity, while the fast carrier transport under tunneling results in high speed. In addition, the photocurrent can be controllably switched from positive to negative values, with ∼104× enhancement in responsivity, by engineering the band alignment from type-II to type-III using either the drain or the gate bias. This is further reinforced by electric-field dependent interlayer band structure calculations using density functional theory. The high negative responsivity of 2 × 104 A/W and fast response time of ∼1 μs coupled with a polarity-tunable photocurrent can lead to the development of next-generation multifunctional optoelectronic devices