Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub‑5 nm Thick Electrostatically Highly Doped Channel

Junctionless transistors are suitable for sub-3 nm applications because of their extremely simple structure and high electrical performance, which compensate for short-channel effects. Two-dimensional semiconductor transition-metal dichalcogenide materials, such as MoS2, may also resolve technical and fundamental issues for Si-based technology. Here, we present the first junctionless electric-double-layer field-effect transistor with an electrostatically highly doped 5 nm thick MoS2 channel. A double-gated MoS2 transistor with an ionic-liquid top gate and a conventional bottom gate demonstrated good transfer characteristics with a 104 on–off current ratio, a 70 mV dec–1 subthreshold swing at a 0 V bottom-gate bias, and drain-current versus top-gate-voltage characteristics were shifted left significantly with increasing bottom-gate bias due to an electrostatically increased overall charge carrier concentration in the MoS2 channel. When a bottom-gate bias of 80 V was applied, a shoulder and two clear peak features were identified in the transconductance and its derivative, respectively; this outcome is typical of Si-based junctionless transistors. Furthermore, the decrease in electron mobility induced by a transverse electric field was reduced with increasing bottom-gate bias. Numerical simulations and analytical models were used to support these findings, which clarify the operation of junctionless MoS2 transistors with an electrostatically highly doped channel

Few-Layer Black Phosphorus Field-Effect Transistors with Reduced Current Fluctuation

We investigated the reduction of current fluctuations in few-layer black phosphorus (BP) field-effect transistors resulting from Al₂O₃ passivation. In order to verify the effect of Al₂O₃ passivation on device characteristics, measurements and analyses were conducted on thermally annealed devices before and after the passivation. More specifically, static and low-frequency noise analyses were used in monitoring the charge transport characteristics in the devices. The carrier number fluctuation (CNF) model, which is related to the charge trapping/detrapping process near the interface between the channel and gate dielectric, was employed to describe the current fluctuation phenomena. Noise reduction due to the Al₂O₃ passivation was expressed in terms of the reduced interface trap density values <i>D</i>_it and <i>N</i>_it, extracted from the subthreshold slope (SS) and the CNF model, respectively. The deviations between the interface trap density values extracted using the SS value and CNF model are elucidated in terms of the role of the Schottky barrier between the few-layer BP and metal contact. Furthermore, the preservation of the Al₂O₃-passivated few-layer BP flakes in ambient air for two months was confirmed by identical Raman spectra

Energy-Efficient III–V Tunnel FET-Based Synaptic Device with Enhanced Charge Trapping Ability Utilizing Both Hot Hole and Hot Electron Injections for Analog Neuromorphic Computing

A charge trap device based on field-effect transistors (FET) is a promising candidate for artificial synapses because of its high reliability and mature fabrication technology. However, conventional MOSFET-based charge trap synapses require a strong stimulus for synaptic update because of their inefficient hot-carrier injection into the charge trapping layer, consequently causing a slow speed operation and large power consumption. Here, we propose a highly efficient charge trap synapse using III–V materials-based tunnel field-effect transistor (TFET). Our synaptic TFETs present superior subthreshold swing and improved charge trapping ability utilizing both carriers as charge trapping sources: hot holes created by impact ionization in the narrow bandgap InGaAs after being provided from the p+-source, and band-to-band tunneling hot electrons (BBHEs) generated at the abrupt p+n junctions in the TFETs. Thanks to these advances, our devices achieved outstanding efficiency in synaptic characteristics with a 5750 times faster synaptic update speed and 51 times lower sub-fJ/um2 energy consumption per single synaptic update in comparison to the MOSFET-based synapse. An artificial neural network (ANN) simulation also confirmed a high recognition accuracy of handwritten digits up to ∼90% in a multilayer perceptron neural network based on our synaptic devices

Brush-Shaped ZnO Heteronanorods Synthesized Using Thermal-Assisted Pulsed Laser Deposition

Brush-shaped ZnO heteronanostructures were synthesized using a newly designed thermal-assisted pulsed laser deposition (T-PLD) system that combines the advantages of pulsed laser deposition (PLD) and a hot furnace system. Branched ZnO nanostructures were successfully grown onto CVD-grown backbone nanowires by T-PLD. Although ZnO growth at 300 °C resulted in core–shell structures, brush-shaped hierarchical nanostructures were formed at 500–600 °C. Materials properties were studied via photoluminescence (PL), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) characterizations. The enhanced photocurrent of a SnO₂–ZnO heterostructures device by irradiation with 365 nm wavelength ultraviolet (UV) light was also investigated by the current–voltage characteristics

Modification of Electrical Properties of Graphene by Substrate-Induced Nanomodulation

A periodically modulated graphene (PMG) generated by nanopatterned surfaces is reported to profoundly modify the intrinsic electronic properties of graphene. The temperature dependence of the sheet resistivity and gate response measurements clearly show a semiconductor-like behavior. Raman spectroscopy reveals significant shifts of the G and the 2D modes induced by the interaction with the underlying grid-like nanostructure. The influence of the periodic, alternating contact with the substrate surface was studied in terms of strain caused by bending of graphene and doping through chemical interactions with underlying substrate atoms. Electronic structure calculations performed on a model of PMG reveals that it is possible to tune a band gap within 0.14–0.19 eV by considering both the periodic mechanical bending and the surface coordination chemistry. Therefore, the PMG can be regarded as a further step toward band gap engineering of graphene devices