Search for dark matter produced in association with bottom or top quarks in √s = 13 TeV pp collisions with the ATLAS detector

A search for weakly interacting massive particle dark matter produced in association with bottom or top quarks is presented. Final states containing third-generation quarks and miss- ing transverse momentum are considered. The analysis uses 36.1 fb−1 of proton–proton collision data recorded by the ATLAS experiment at √s = 13 TeV in 2015 and 2016. No significant excess of events above the estimated backgrounds is observed. The results are in- terpreted in the framework of simplified models of spin-0 dark-matter mediators. For colour- neutral spin-0 mediators produced in association with top quarks and decaying into a pair of dark-matter particles, mediator masses below 50 GeV are excluded assuming a dark-matter candidate mass of 1 GeV and unitary couplings. For scalar and pseudoscalar mediators produced in association with bottom quarks, the search sets limits on the production cross- section of 300 times the predicted rate for mediators with masses between 10 and 50 GeV and assuming a dark-matter mass of 1 GeV and unitary coupling. Constraints on colour- charged scalar simplified models are also presented. Assuming a dark-matter particle mass of 35 GeV, mediator particles with mass below 1.1 TeV are excluded for couplings yielding a dark-matter relic density consistent with measurements

Electronics Design and System Integration of the ATLAS New Small Wheels

The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will allow to in-crease the luminosity to 2×1034 cm−2s−1 and 5-7×1034 cm−2s−1, respectively. For the HL-LHC phase, the expected mean number of interactions per bunch crossing will be 55 at 2×1034 cm−2s−1 and ~140 at 5×1034 cm−2s−1. This increase drastically impacts the ATLAS trigger and trigger rates. For the ATLAS Muon Spectrometer, a replacement of the innermost endcap stations, the so-called “Small Wheels” operating in a magnetic field, is therefore planned for 2019/20 to be able to maintain a low pT threshold for single muon and excellent tracking capability in the HL-LHC regime. The New Small Wheels will feature two new detector technologies: Resistive Micromegas and small strip Thin Gap Chambers comprising a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives fully compliant with the post-2024 HL-LHC operation. To al-low for some safety margin, the design studies assume a maximum instantaneous luminosity of 7×1034 cm−2 s−1, 200 pile-up events, trigger rates of 1 MHz at Level-0 and 400 KHz at Level-1. A radia-tion dose of ~1700 Gy (inner radius) is expected. The electronics design of such a system will be implemented in some 8000 on-detector boards including the design of four different custom ASICs. Among them the 64-channel VMM, a common frontend mixed-signal ASIC for both detector tech-nologies and charge-interpolating trackers, provides amplitude and timing measurements, direct output of trigger primitives and Level-0 trigger buffering. The candidate selection is required to be within a budget latency of 1 us, and 6 us after 2024. Moreover, the design integrates the GBTx (a radiation hard 5 Gigabit transceiver) and a Slow Control ASICs developed at CERN. The custom GBTx data flow links are aggregated onto an industry standard high speed network to which standard PCs perform data acquisition, configuration, and monitoring. The large number of readout channels, high speed output data rate, harsh radiation and magnetic environment, small available space, poor access and low power consumption all impose great challenges on the system design. The overall design and first results from integration of the electronics in a vertical slice test will be presented

Level-1 Data Driver Card of the ATLAS New Small Wheel upgrade

The Level-1 Data Driver Card (L1DDC) will be fabricated for the needs of the future upgrades of the ATLAS experiment at CERN. Specifically, these upgrades will be performed in the innermost stations of the muon spectrometer end-caps. The L1DDC board is a high speed aggregator board capable of communicating with a large number of front-end electronics. It collects the Level-1 along with monitoring data and transmits them to a network interface through a single bidirectional fibre link. Finally, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. This paper describes the overall scheme of the data acquisition process and especially the L1DDC board for the upgrade of the New Small Wheel. Finally, the electronics layout on the chamber is also mentioned

Level-1 Data Driver Card of the ATLAS New Small Wheel upgrade compatible with the Phase II 1 MHz readout scheme

The Level-1 Data Driver Card (L1DDC) will be designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. The L1DDC is a high speed aggregator board capable of communicating with a large number of front-end electronics. It collects the Level-1 data along with monitoring data and transmits them to a network interface through a single bidirectional fiber link. In addition, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. The L1DDC is fully compatible with the Phase II upgrade where the trigger rate is expected to reach 1 MHz. This paper describes the overall scheme of the data acquisition process and especially the L1DDC board. Finally, the electronics layout on the chamber is also mentioned

NSW

NSW electronics description, integration, calibration, configuration, issues and solutions

LEVEL-1 DATA DRIVER CARD (L1DDC) OF THE NEW SMALL WHEEL ATLAS EXPERIMENT

Poster for the IEEE, San Diego 201

Design and development of the Level-1 Data Driver Card (L1DDC) for the New Small Wheel upgrade of the ATLAS experiment at CERN

ATLAS is one of the four main experiments located in the Large Hardon Collider at CERN. During Long Shutdown 2 (2019-2020) the innermost muon stations of ATLAS called the Small Wheels will be replaced by the New Small Wheel upgrade project. This upgrade is motivated by the high particle flux (up to 15 kHz/cm2), the high radiation during Run-3 (2021-2023) and ultimate luminosity of 7.5 × 10^(34) cm^(-2) s^-1 expected in High-Luminosity Large Hadron Collider (after 2026). The number of interactions per bunch-crossing (every 25 ns) will be increased upto 140, resulting in a dramatically large amount of produced data. The New Small Wheel is a set of precision tracking and trigger detectors able to work at high rates with excellent real-time spatial and time resolution. The new detectors consist of the resistive Micromegas and the small-strip Thin Gap Chambers. Furthermore, a radiation dose up to 1700 Gy (innermost radius) and a magnetic field up to 0.4 T in the end cap region, create a hostile environment for the front-end electronics. To read out the large number of electronic channels (~2.1 million for the Micromegas and ∼332 thousand for the sTGC) and in order to survive in such a harsh envi- ronment new electronics must be fabricated and installed. In addition, correction mechanisms for Single Event Upsets (this is a change of state caused by a high-energy particle strike to a micro-electronic device) must be implemented to assure the integrity of the transmitted data. The whole readout and trigger architecture of the NSW was redesigned including the fabrication of new electronic boards and Application Specific Integrated Circuits compatible even with the Run-4 data rates. The aim of this dissertation was the research and development of the Level-1 Data Driver Card which is part of the data acquisition system for both detector technologies and consists of radiation tolerant components. The development of the cards included a series of prototypes and their extensive testing independently, and as part of the final system as well. A major and extensive study to make these cards compatible even with the future (and demanding) upgrades of the experiment was performed. Up to now, eight different versions of these cards have been manufactured and tested. The latest prototypes, after their debugging, are the reference cards for mass production of 1056 Level-1 Data Driver Cards. Additionally for the needs of the experiment and for a more complete control and testing of the cards and the final system, a series of Front-Ends, a Low Voltage distributor and a series of auxiliary cards were designed and fabricated. Furthermore for the testing procedure of the boards different pieces of firmware were de- veloped using the Very High Speed Integrated Circuit Hardware Description Language. This development includes communication of the control system with the Level-1 Data Driver Card through optical link, the programming of the Application Specific Integrated Circuits on the Level-1 Data Driver Card card, the acquisition of environmental variables (voltage levels and temperatures) and their evaluation by a personal computer through the Ethernet interface and UDP/IP protocols. In order to validate the final system, a low-level code was also developed, tested and debugged to configure the Venetis MicroMegas Application Specific Integrated Cir- cuit (on the Front-Ends) to collect data from the detectors and transfer them via the UDP/IP protocol to a computer for storage and subsequent evaluation

Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the front-end readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10/100/1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micromegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies will be described

Level-1 Data Driver Card - A high bandwidth radiation tolerant aggregator board for detectors

The Level-1 Data Driver Card (L1DDC) was designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. The L1DDC is a high speed aggregator board capable of communicating with multiple front-end electronic boards. It collects the Level-1 data along with monitoring data and transmits them to a network interface through bidirectional and/or unidirectional fiber links at 4.8 Gbps each. In addition, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. The L1DDC is fully compatible with the Phase II upgrade where the trigger rate is expected to reach the 1 MHz. Three different types of L1DDC boards will be fabricated handling up to 10.080 Gbps of user data. It consist of custom made radiation tolerant ASICs: the GigaBit Transceiver (GBTx), the FEAST DC-DC converter, the Slow Control Adapter (SCA), and the Versatile Tranceivers (VTRX) and transmitters (VTTX). The overall scheme of the data acquisition process and in particular the L1DDC board will be described. The results from the various system integration and radiation tests will be presented

Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the frontend readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10=100=1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micormegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies will be described