11 research outputs found

    Methodology for standard cell compliance and detailed placement for triple patterning lithography

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    As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition

    E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System

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    Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic node. To overcome its throughput limitation, recently the traditional EBL system is extended into MCC system. %to further improve the throughput. In this paper, we present E-BLOW, a tool to solve the overlapping aware stencil planning (OSP) problems in MCC system. E-BLOW is integrated with several novel speedup techniques, i.e., successive relaxation, dynamic programming and KD-Tree based clustering, to achieve a good performance in terms of runtime and solution quality. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both conventional EBL system and MCC system

    A New Global Router for Modern Designs

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    Abstract -In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhance our global router. These techniques include (1) a history based cost function which helps to distribute overflow during iterative rip-ups and reroutes, (2) an adaptive multi-source multi-sink maze routing method to improve the wirelength of maze routing, (3) a congested region identification method to specify the order for nets to be ripped up and rerouted, and (4) a refinement process to further reduce overflow when iterative history based rip-ups and reroutes reach bottleneck. Compared with two state-of-the-art works on ISPD98 benchmarks, NTHU-Route outperforms them in both overflow and wirelength. For the much larger designs from the ISPD07 benchmark suite, our solution quality is better than or comparable to the best results reported in the ISPD07 routing contest. I Introduction In the recent years, feature size continues to shrink. Although the device becomes smaller and faster, the shrinkage increases the wire resistance and hence interconnect delay. Interconnect delay has replaced transistor delay as the main determinant of chip performance. Therefore the routing problem is becoming even more important in VLSI design. Typically, the routing problem can be divided into two steps due to the problem complexity: global routing and detailed routing. During global routing, nets are connected on a coarse-grain grid graph with capacity constraints. Then detailed routing follows the solution in global routing to find the exact routing solution. The quality of global routing affects timing, power and density in the chip area, and thus global routing is a very important stage in the design cycle. Recent global routing techniques can be roughly categorized into two classes: multicommodity flow based techniques and rip-up and reroute techniques. Multicommodity flow based techniques Rip-up and reroute approach starts by routing each net without considering congestion. After routing all nets, congested areas can be identified and the nets in those areas are ripped up and rerouted to find less congested routes. This approach is a sequential one since the net to be ripped up and rerouted has to follow a specific order. Therefore the routing order in rip-up and reroute techniques affects the solution quality a lot. Chi Dispersion In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhance our global router. These techniques include (1) a history based cost function which helps to distribute overflow during iterative rip-ups and reroutes, (2) an adaptive multi-source multi-sink maze routing method to improve the wirelength of maze routing, (3) a congested region identification method to specify the order for nets to be ripped up and rerouted, and (4) a refinement process to further reduce overflow when iterative history based rip-ups and reroutes reach bottleneck. We compare our results with two state-of-the-art works, BoxRouter and FastRoute, on ISPD98 benchmarks. Our global router solves all benchmarks without any overflow and respectively reduces the wirelength over BoxRouter and FastRoute by 1.93% and 2.59% on average. We also perform our router on ISPD07 benchmarks which contain multi-layer designs with larger size. The experiments show that our router obtains the solution with least overflow when comparing with the best results reported in the ISPD07 global routing contest. The rest of the paper is organized as follows. Section II gives the preliminaries including the problem formulation and introduction for some routing techniques. In section III, we present our global router in detail. Section IV provides the experimental results and we conclude the paper in section V

    3A-4 A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction *

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    tree (RSMT) is a fundamental problem. Today’s design often contains rectilinear obstacles, like macro cells, IP blocks, and pre-routed nets. Therefore obstacle-avoiding RSMT (OARSMT) construction becomes a very practical problem. In this paper we present a fast and stable algorithm for this problem. We use a partitioning based method and an ant colony optimization based method to construct obstacle-avoiding Steiner minimal tree (OASMT). Besides, two heuristics are proposed to do the rectilinearization and refinement to further improve wirelegnth. The experimental results show our algorithm achieves the best wirelength results in most of the test cases and the runtime is very small even for the larger cases each of which has both the number of terminals and the number of obstacles more than 100. I

    EBL overlapping aware stencil planning for MCC system

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    © 2016 ACM. Electron beam lithography (EBL) is a promising, maskless solution for the technology beyond 14nm logic nodes. To overcome its throughput limitation, industry has proposed character projection (CP) technique, where some complex shapes (characters) can be printed in one shot. Recently, the traditional EBL system was extended into a multi-column cell (MCC) system to further improve the throughput. In an MCC system, several independent CPs are used to further speed-up the writing process. Because of the area constraint of stencil, the MCC system needs to be packed/planned carefully to take advantage of the characters. In this article, we prove that the overlapping aware stencil planning (OSP) problem is NP-hard. Then we propose E-BLOW, a tool to solve the MCC system OSP problem. E-BLOW involves several novel speedup techniques, such as successive relaxation and dynamic programming. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both the conventional EBL system and the MCC system
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