64 research outputs found

    Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking

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    Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.Comment: 91 pages, 67 figures, 11 tables. Related to the conference presentation D. Nikonov and I. Young, Uniform Methodology for Benchmarking Beyond-CMOS Logic Devices, Proceedings of IEDM, 25.4 (2012

    Spin Gain Transistor in Ferromagnetic Semiconductors: the Semiconductor Bloch Equations Approach

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    Scheme and principle of operation of a spin gain transistor are proposed: a large unmagnetized current creates density sufficient for the ferromagnetic transition; a small magnetized current initiates spontaneous magnetization; large magnetized current is extracted. Therefore spin gain of more than 1000 is predicted. Collective dynamics of spins under Coulomb exchange interaction is described via Semiconductor Bloch Equations.Comment: 34 pages, PDF fil

    Role of Phonon Scattering in Graphene Nanoribbon Transistors: Non-Equilibrium Green's Function Method with Real Space Approach

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    Mode space approach has been used so far in NEGF to treat phonon scattering for computational efficiency. Here we perform a more rigorous quantum transport simulation in real space to consider interband scatterings as well. We show a seamless transition from ballistic to dissipative transport in graphene nanoribbon transistors by varying channel length. We find acoustic phonon (AP) scattering to be the dominant scattering mechanism within the relevant range of voltage bias. Optical phonon scattering is significant only when a large gate voltage is applied. In a longer channel device, the contribution of AP scattering to the dc current becomes more significant

    Circuit Theory for SPICE of Spintronic Integrated Circuits

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    We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We propose an extension to the Modified Nodal Analysis technique for the analysis of spin circuits based on the recently developed spin conduction matrices. We demonstrate the applicability of the framework using an example spin logic circuit described using spin Netlists.Comment: 14 pages, 11 figures; added fig. 2; added citations; modified title to emphasize SPICE; Results unchange

    Proposal of a spin torque majority gate logic

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    A new spin based logic device is proposed. It is comprised of a common free ferromagnetic layer separated by a tunnel junction from three inputs and one output with separate fixed layers. It has the functionality of a majority gate and is switched by spin transfer torque. Validity of its logic operation is demonstrated by micromagnetic simulation. A version of such devices with perpendicular magnetization is examined. Switching encompasses moving domain walls. The device reuses most of the materials and structures from spin torque RAM, and is entirely compatible with CMOS technology.Comment: 14 pages, 4 figure

    Material Targets for Scaling All Spin Logic

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    All-spin logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to non-volatility, ultra-low operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin logic devices that can surpass energy-delay performance of CMOS transistors. With validated stochastic nano-magnetic and vector spin transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identified promising new directions for material engineering/discovery focusing on systematic scaling of magnetic anisotropy (Hk) with saturation magnetization (Ms), use of perpendicular magnetic anisotropy, and interface spin mixing conductance of ferromagnet/spin channel interface (Gmix). We provide systematic targets for scaling spin logic energy-delay product toward a 2 aJ.ns energy-delay product, comprehending the stochastic noise for nanomagnets.Comment: 21 pages, 8 figure

    All Spin Nano-magnetic State Elements

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    We propose an all spin state element to enable all spin state machines using spin currents and nanomagnets. We demonstrate via numerical simulations the operation of a state element a critical building block for synchronous, sequential logic computation. The numerical models encompass Landau-Lifshitz-Gilbert (LLG) nanomagnet dynamics with stochastic models and vector spin-transport in metallic magnetic and non-magnetic channels. Combined with all spin combinatorial logic, the state elements can enable synchronous and asynchronous computing elements.Comment: 21 pages, 6 figure

    Patterns and Thresholds of Magnetoelectric Switching in Spin Logic Devices

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    In the quest to develop spintronic logic, it was discovered that magnetoelectric switching results in lower energy and shorter switching time than other mechanisms. Magnetoelectric (ME) field due to exchange bias at the interface with a multi-ferroic (such as BiFeO3) is well suited for 180 degree switching of magnetization. The ME field is determined by the direction of canted magnetization in BiFeO3 which can point at an angle to the plane, to which voltage is applied. Dependence of switching time and the threshold of ME field on its angles was determined by micromagnetic simulations. Switching occurs by formation of a domain wall on the side of the nanomagnet on top of BFO and its propagation to the rest of the magnet. For in-plane magnetization, switching occurs over a wide range of angles and at all magnitudes of ME field above threshold. For out-of-plane magnetization failure occurs (with an exception of a narrow range of angles and magnitudes of ME field) due to the domain wall reflecting from the opposite end of the nanomagnet.Comment: 7 pages, 5 figure

    Voltage and Energy-Delay Performance of Giant Spin Hall Effect Switching for Magnetic Memory and Logic

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    In this letter, we show that Giant Spin Hall Effect (GSHE) MRAM can enable better energy- delay and voltage performance than traditional MTJ based spin torque devices at scaled nanomagnet dimensions (10-30 nm). Firstly, we derive the effect of dimensional scaling on spin injection efficiency, voltage-delay and energy-delay of spin torque switching using MTJs and GSHE and identify the optimum electrode geometry for low operating voltage (10 GHz) operation. We show that effective spin injection efficiency >100 % can be obtained using optimum spin hall electrode thickness for 30 nm nanomagnet widths. Finally, we derive the energy-delay trajectory of GSHE and MTJ devices to calculate the energy-delay product of GSHE and MTJ devices with an energy minimum at the characteristic time of the magnets. Optimized GSHE devices when combined with PMA can enable MRAM with scaled nanomagnets (30 nm X 60 nm), ultra-low voltage operation (< 0.1 V), fast switching times (10 ps) and switching energy as low as 100 aJ/bit.Comment: 16 pages, 5 figure

    Convolutional Networks for Image Processing by Coupled Oscillator Arrays

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    A coupled oscillator array is shown to approximate convolutions with Gabor filters for image processing tasks. Pixelated image fragments and filter functions are converted to voltages, differenced, and input into a corresponding array of weakly coupled Voltage Controlled Oscillators (VCOs). This is referred to as Frequency Shift Keying (FSK). Upon synchronization of the array, the common node amplitude provides a metric for the degree of match between the image fragment and the filter function. The optimal oscillator parameters for synchronization are determined and favor a moderate value of the Q-factor.Comment: 23 pages, 12 figure
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