VHDL synthesis system (VSS) : user's manual, version 5.0

This report provides instructions for installing and using the VHDL Synthesis System (Version 5.0). VSS is a high level synthesis sytem that synthesizes structures from an abstract description, written with VHDL behavioral constructs. The system uses components from a generic component library (GENUS). The output of VSS is in structural VHDL and could be verified using a commercial VHDL simulator. The designer can control the synthesis process by providing different resource constraints to the system. VSS is also capable of producing different architectures which can be selected by the designer

Layout area models for high-level synthesis

Traditionally, the common cost functions, the number of functional units, registers and selector inputs, are used in high level synthesis as quality measures. However, these traditional design quality measures may not reflect the real physical design. To establish quality measures based on the physical designs, we propose layout estimation models for two commonly used data path and control layout architectures. The results show that quality measures deriving from our models give an accurate prediction of the final layout. The results also show that traditional cost functions are not good indicators for optimization in high level synthesis

Back-annotation for interactive data path synthesis

In order to take into account physical design effects, a designer needs a feedback mechanism during interactive data path synthesis. In this paper, we propose a hypergraph model and a back-annotation algorithm which provide a feedback mechanism for back-annotation from physical designs to behavioral descriptions. Given a control data flow graph and its structural design, this back-annotation technique cannot only evaluate the design quality but can also feedback the delay to each edge and node in the graph. Therefore, a designer can identify the critical paths and improve the design. The hypergraph model and the back-annotation algorithm allow us to bridge the gap between the behavioral description and the physical design

Timing models for high-level synthesis

In this paper, we describe a timing model for clock estimation during high-level synthesis. In order to obtain realistic timing estimates, the proposed model considers all delay elements, including datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices must be rapidly and incrementally calculated

A VLSI implementation of the collision avoidance switch protocol for CAMB tree LANs

To solve a performance bottle neck in random access LANs due to packet collisions and their resolution, collision avoidance switches are introduced. These switches allow random access protocols to achieve high performance by resolving collisions among packets. A conventional hardware implementation of these switches is the use of TTL chips. In this implementation; a handful of TTL chips are required to forma single switch (e.g., 18 TTL chips are needed for an implementation of the CAMB switch [7]). Thus, implementation of a complete network, which requires several of these switches, could very well result in a large and complex hardware system.Today's modern chip technology allows us to pack large quantity of logic in a single chip. By transferring the conventional implementation of the collision avoidance switches into a VLSI chip, the complexity of the resultant hardware is greatly reduced, not to mention the improvement in hardware performance and ease of packaging.This report provides an overall study of the collision avoidance protocols for the tree LANs with emphasis on the implementation of collision avoidance switches. Hardware implementations of sorne of these switches are discussed. And a VLSI implementation of the CAMB switch protocol is introduced

Assignment Decision Diagram for High-Level Synthesis

In the past, the research on representation for synthesis systems had been focusing on two main issues, the completeness and the efficiency. There is, however, another important issue that is not addressed by most of traditional representations, the uniqueness. This report proposes a representation for synthesis called the Assignment Decision Diagram (ADD) that is complete, efficient and partially unique. In addition, the ADD also furnishes many synthesis tasks with information that can simplify the tasks, and can enrich the results of the synthesis. Discussion of ADD's properties and its uses in synthesis is provided in this report. Contents 1 Introduction 5 2 Assignment Decision Diagrams (ADD) 6 3 Representing behavior and structure information in the Assignment Decision Diagrams 10 3.1 Representing behavior information in the ADD : : : : : : : : : : : : : : : : : : 10 3.1.1 Variable type : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 10 3.1.2 Assignment con..

Minimizing syntactic variance with assignment decision diagrams

Most synthesis systems generate designs from hardware descriptions by relating each language construct to a particular hardware structure. Thus, designs obtained from these systems are dependent on description styles. In other words, semantically equivalent descriptions with different ordering or grouping of conditional and assignment statements, could generate designs with distinctively diff erent cost and performance. This paper introduces a new representation that minimizes the syntactic variance of different description styles. We also propose an algorithm for conversion of hardware descriptions into this new representation. In addition, using this representation for scheduling results in a drastic reduction on the number of control steps required to synthesize the description. Experimental data on severa[ examples show effectiveness ofthe proposed approach