High-speed driver and receiver electronics for next-generation optical networks

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Evaluation of a discrete 4-PAM optical link for future automotive networks

A comparative study is presented between NRZ and 4-PAM to investigate the feasibility of Gigabit transmission in automotive optical networks. The system utilizes a SI-PCS fiber and an 850 nm VCSEL as transmitter. Laser driver and receiver are realized with discrete transistors at board level. Eye diagram measurements reveal that 4-PAM outperforms NRZ using 1m and 6m of fiber. Bitrates of 2 Gb/s are achieved at a BER ≤ 100000. Covering longer distances shows that SI-PCS introduces severe dispersion. Therefore, GI-PCS fiber is suggested as optical link for future automotive networks

Implementation of the dissection theorem in cadence virtuoso

This paper describes a tool for the Cadence Virtuoso software that implements the Dissection Theorem (DT) or General Network Theorem (GNT) and its applications: the Extra Element Theorem (EET), Chain Theorem (CT) and General Feedback Theorem (GFT). The tool allows a circuit designer to gain additional circuit insight by providing all second- and third-level transfer functions of the DT. In particular, feedback networks are factored into their exact components, enabling a deeper insight into the structure of the loop gain, direct forward transmission and hence closed-loop behaviour

Efficient implementation of 90 degrees phase shifter in FPGA

In this article, we present an efficient way of implementing 90 phase shifter using Hilbert transformer with canonic signed digit (CSD) coefficients in FPGA. It is implemented using 27-tap symmetric finite impulse response (FIR) filter. Representing the filter coefficients by CSD eliminates the need for multipliers and the filter is implemented using shifters and adders/subtractors. The simulated results for the frequency response of the Hilbert transformer with infinite precision coefficients and CSD coefficients agree with each other. The proposed architecture requires less hardware as one adder is saved for the realization of every negative coefficient compared to convectional CSD FIR filter implementation. Also, it offers a high accuracy of phase shift

A digitally controlled threshold adjustment circuit in a 0.13um SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13µm SiGe BiCMOS technology and a threshold tunable between ±160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a data rate of up to 80Gbps can be achieved

A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages

Performance assessment of optical packet switching system with burst-mode receivers for intra-data centre networks

We investigate the performance of a burst-mode receiver in an optical packet switching system. Experimental results indicate that a preamble of 25.6ns allows error-free operation of 10Gb/s asynchronous switched packets with 8dB dynamic range and 25ns minimum guard-time