A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages

Low field vertical charge transport in the channel and buffer layers of GaN-on-Si high electron mobility transistors

Substrate ramps and stepped stress transient measurements are applied to study vertical charge transport mechanisms in GaN-on-Si power HEMTs. By choosing appropriate bias points for substrate stress it is possible to single out the dominant charge transportmechanism: at low negative biases transport through carbon-doped GaN manifests itself in negative (decreasing) current transients with apparent activation energy (E-A) = 0.29 eV, while at larger negative voltages transport through unintentionally doped GaN is characterized by positive (increasing) current transients (E-A = 0.38 eV). We present experimental evidence for 3D variable range hopping taking place in C-doped GaN and 1D hopping along the dislocations in unintentionally doped GaN. By investigating transients obtained from bidirectional voltage steps of 10 V potential difference in the range 0 to -140 V, we observe that hopping transport through dislocations shows non-Ohmic behavior at low substrate biases, which manifests itself in a time constant tau strongly dependent on bias. We propose that this can be explained by the existence of a diode junction between the dislocation core and the 2D electron gas (2DEG)

Surface-potential-based compact model for the gate current of p-GaN Gate HEMTs

The gate leakage current of p-GaN gate HEMTs is modeled based on surface potential calculations. The model accurately describes the bias and temperature dependence of the gate leakage. Thermionic emission is the main mechanism of the gate current in forward bias operation while hopping transport component is the main mechanism of gate current in reverse bias operation. This newly developed gate current model was implemented in Verilog-A. A good agreement between the simulations and experimental data demonstrates the accuracy of the model

Observation of dynamic V-TH of p-GaN Gate HEMTs by fast sweeping characterization

In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the V-TH instability of p-GaN gate HEMTs. As the I-D-V-G sweeping time deceases from 5 ms to 5 mu s, the V-TH dramatically degenerates from 3.13 V to 1.76 V, meanwhile the hysteresis deteriorates from 22.6mV to 1.37 V. Positive bias temperature instability (PBTI) measurement by fast sweeping shows the V-TH features a very fast shifting process but a slower recovering process. D-mode HEMTs counterpart without Mg contamination demonstrates a negligible V-TH shift and hysteresis, proving the V-TH instability is probably due to the ionization of acceptor-like traps in the p-GaN depletion region. Finally, the V-TH instability is verified by a GaN circuit under switching stress. The V-TH instability under different sweeping speed uncovers the fact that the high V-TH by conventionally slow DC measurements is probably artificial. The DC V-TH should be high enough to avoid HEMT faulty turn-on

Charge Transport in GaN High Electron Mobility Transistor With Positive Substrate Bias

Charge transport in 650-V-rated GaN high electron mobility transistors (HEMTs) was investigated using positive substrate bias up to +600 V. Positive substrate bias resulted in a reduction in channel current, attributed to negative charge storage in the buffer, resulting in up to a >50% reduction in the 2-D electron gas (2DEG) channel density. The dynamics of the accumulated charge was investigated using recovery transients after substrate bias stress, with recovery times >1000 s for substrate stress bias >+200 V. The recovery time was reduced significantly with the application of a negative substrate bias of short duration, immediately following the positive substrate bias stress. A comprehensive explanation is presented, which requires a detailed understanding of the transport (both ohmic and non-ohmic) through each of the layers in the epitaxial stack

Use of Bilayer gate insulator in GaN-on-Si Vertical Trench MOSFETs : impact on performance and reliability

We propose to use a bilayer insulator (2.5 nm Al2O3 + 35 nm SiO2) as an alternative to a conventional uni-layer Al2O3 (35 nm), for improving the performance and the reliability of GaN-on-Si semi vertical trench MOSFETs. This analysis has been performed on a test vehicle structure for module development, which has a limited OFF-state performance. We demonstrate that devices with the bilayer dielectric present superior reliability characteristics than those with the uni-layer, including: (i) gate leakage two-orders of magnitude lower; (ii) 11 V higher off-state drain breakdown voltage; and (iii) 18 V higher gate-source breakdown voltage. From Weibull slope extractions, the uni-layer shows an extrinsic failure, while the bilayer presents a wear-out mechanism. Extended reliability tests investigate the degradation process, and hot-spots are identified through electroluminescence microscopy. TCAD simulations, in good agreement with measurements, reflect electric field distribution near breakdown for gate and drain stresses, demonstrating a higher electric field during positive gate stress. Furthermore, DC capability of the bilayer and unilayer insulators are found to be comparable for same bias points. Finally, comparison of trapping processes through double pulsed and V-th transient methods confirms that the V-th shifts are similar, despite the additional interface present in the bilayer devices

Epitaxial buffer structures grown on 200 mm engineering substrates for 1200 V E-mode HEMT application

This project has received funding from the "Electronics Components and Systems for European Leadership" Joint Undertaking (ECSEL JU) under Grant Agreement No. 783174. The JU receives support from the European Union's Horizon 2020 research and innovation program from Austria, Spain, Belgium, Germany, Slovakia, Italy, Netherlands, and Slovenia