Ferroelectric Domain Wall Delayer and Low-Dropout Regulator

A switching-type power converter providing an accurate and stable switching output voltage against line/load variations and power supply ripple is mostly complicated in system-on-chip power management integrated circuits (PMICs) within a limited occupation area. Here we fabricated domain wall (DW) nanodevices using an X-cut LiNbO3 thin film on silicon. The domain switching event occurs after a delay time predicted by Merz’s law under the applied voltage. But the output current is irrespective of the applied voltage and can be adjusted by conducting wall width as well as input resistance in the circuit. The regulating currents appear repetitively across the volatile interfacial domains between the nanodevice and electrode under intermittently applied voltages. A wall-current-limited domain switching model is developed to explain the phenomenon. The multifunctional DW nanodevices with smaller occupation areas can serve as compact low-dropout regulators in PMICs, time-domain delayers in energy-efficient neural network systems, and on-chip electrostatic discharge protection besides nonvolatile memories and selectors

Hybrid Dry and Wet Etching of LiNbO₃ Domain-Wall Memory Devices with 90° Etching Angles and Excellent Electrical Properties

Ferroelectric domain walls, agile nanoscale interfaces of polar order, can be selectively controlled by electric fields for their position, conformation, and function, which is ultimately the key to realizing novel low-energy memory and computing structures. LiNbO3 single-crystal domain wall memory has the advantages of high operational speed, high integration density, and virtually unlimited endurance cycles, appearing as a good solution for the next generation of highly miniaturized low-energy memories. However, the etching process poses significant challenges in the nanofabrication and high-density integration of LiNbO3 domain-wall memories. Here, we employed a hybrid etching technique to achieve smooth sidewalls with a 90° inclined angle, leading to a 24% reduction in the coercive field and a 2.5-fold increase in the linear domain wall current density with a retention time of more than 106 seconds and endurance of over 105 writing cycles. Combined with the results of X-ray diffraction patterns and X-ray photoelectric spectra, it is concluded that the excellent electrical performance is related to the formation of an oxygen-deficient LiNbO3–x layer on the sidewall surface during the wet chemical etching process, which is a conductive layer that reduces the thickness of the “dead” layer between the side electrodes and the LiNbO3 cell and rectifies the diode-like wall currents with an onset voltage reduced from 1.23 to 0.28 V. These results prove the high-density integration of ferroelectric domain-wall memories at the nanoscale and provide a new strategy applicable to the development of LiNbO3 photonic devices