Digital synchronizer Patent

Digital synchronizer for extracting binary data in receiver of PSK/PCM communication syste

Binary Number Sorter-Patent

Binary number sorter for arranging numbers in order of magnitud

Block encoders for Reed-Muller codes

Encoding algorithms generate a 32 x 64-bit matrix Reed-Muller code from a 6-bit orthogonal code-word. This increases error-free reception by a high rate telemetry channel under adverse signal noise with minimal use of additional hardware

Frequency control circuit for all-digital phase-lock loops

Phase-lock loop references all its operations to fixed high-frequency service clock operating at highest speed which digital circuits permit. Wide-range control circuit provides linear control of frequency of reference signal. It requires only two counters in combination with control circuit consisting only of flip-flop and gate

Simple first order data compression processor concept

Data-compression processing systems based on an analog-to-digital converter /ADC/, includes a qualitative comparator for comparison of the ADC output with a ramp generator, which is connected as a bidirectional binary counter with selective inputs. A bidirectional ramp counter selects the proper ramp through a ramp generator selection network

Ranging system Patent

Spacecraft ranging syste

Monitoring system determines amplitude and time of vibration channel peaks

Adaptive scheme advocated in this innovation will reduce processing time and is applicable to environmental testing and to space-borne or aircraft-borne vibration monitoring devices requiring a large number of channels

Decoder system Patent

Binary data decoding device for use at receiving end of communication channe

Systems of coding and their implementation

Engineering planning document surveys mechanics, utility, and potential improvements of codes which control noise-generated errors introduced into radio transmission of binary information. Chronological development of certain codes and a comprehensive bibliography are included

Simplified, reliable circuit sorts binary numbers in order of magnitude

Circuit includes a single-word input/output register and a multiword serial memory which are circulated in synchronism. It puts out data at a rate compatible with relatively slow-speed electromechanical devices