Toward an active CMOS electronics-photonics platform based on subwavelength structured devices

The scaling trend of microelectronics over the past 50 years, quantified by Moore’s Law, has faced insurmountable bottlenecks, necessitating the use of optical communication with its high bandwidth and energy efficiency to further improve computing performance. Silicon photonics, compatible with CMOS platform manufacturing, presents a promising means to achieve on-chip optical links, employing highly sensitive microring resonator devices that demand electronic feedback and control due to fabrication variations. Achieving the full potential of both technologies requires tight integration to realize the ultimate benefits of both realms of technology, leading to the convergence of microelectronics and photonics. A promising approach for achieving this convergence is the monolithic integration of electronics and photonics on CMOS platforms. A critical milestone was reached in 2015 with the demonstration of the first microprocessor featuring photonic I/O (Chen et al, Nature 2015), accomplished by integrating transistors and photonic devices on a single chip using a monolithic CMOS silicon-on-insulator (SOI) platform (GlobalFoundries 45RFSOI, 45 nm SOI process) without process modifications, thus known as the "zero-change" approach. This dissertation focuses on leveraging the fabrication capabilities of advanced monolithic electronic-photonic 45 nm CMOS platforms, specifically high-resolution lithography and small feature size doping implants, to realize photonic devices with subwavelength features that could potentially provide the next leap in integrated optical links performance, beyond microring resonator based links. Photonic crystal (PhC) nanobeam cavities can support high-quality resonance modes while confining light in a small volume, enhancing light-matter interactions and potentially enabling ultimate efficiencies in active devices such as modulators and photodetectors. However, PhC cavities have been overshadowed by microring resonators due to two challenges. First, their fabrication demands high lithography resolution, which excludes most standard SOI photonic platforms as viable options for creating these devices. Secondly, the standing-wave nature of PhC nanobeam cavities complicates their integration into wavelength-division multiplexing (WDM) optical links, causing unwanted reflections when coupled evanescently to a bus waveguide. In this work, we present PhC nanobeam cavities with the smallest footprint, largest intrinsic quality factor, and smallest mode volume to be demonstrated to date in a monolithic CMOS platform. The devices were fabricated in a 45 nm monolithic electronics–photonics CMOS platform optimized for silicon photonics, GlobalFoundries 45CLO, exhibiting a quality factor in excess of 100,000 the highest among fully cladded PhC nanobeam cavities in any SOI platform. Furthermore to eliminate reflections, we demonstrate an approach using pairs of PhC nanobeam cavities with opposite spatial mode symmetries to mimic traveling-wave-like ring behavior, enabling efficient and seamless WDM link integration. This concept was extended to realize a reflectionless microring resonator unit with two microrings operating as standing-wave cavities. Using this scheme with standing-wave microring resonators could lead to an optimum geometry for microring modulators with interdigitated p-n junctions in terms of modulation efficiency in a manner that allows for straightforward WDM cascading. This work also presents the first demonstration of resonant-structure-based modulators in the GlobalFoundries 45CLO platform. We report the first-ever demonstration of a PhC modulator in a CMOS platform, featuring a novel design with sub-wavelength contacts on one side allowing it to benefit from the "reflection-less"' architecture. Additionally, we also report the first demonstration of microring modulators. The most efficient devices exhibited electro-optical bandwidths up to 30 GHz, and 25 Gbps non-return-to-zero (NRZ) on-off-keyed (OOK) modulation with 1 dB insertion loss and 3.1 dB extinction ratio. Finally, as the complexity of silicon photonic systems-on-a-chip (SoC) increases to enable new applications such as low-energy data links, quantum optics, and neuromorphic computing, the need for in-situ characterization of individual components becomes increasingly important. By combining Near-field scanning optical microscopy (NSOM) with a flip-chip post-processing technique, this dissertation demonstrates a method to non-invasively perform NSOM scans of a photonic device within a large-scale CMOS-photonic circuit, without interfering with the performance and packaging of the photonics and electronics, making it a valuable tool for future development of high performance photonic circuits and systems

Vernier optical phased array lidar transceivers

Optical phased arrays (OPAs) which beam-steer in two dimensions (2D) are currently limited to grating row spacings well above a half wavelength. This gives rise to grating lobes along one axis which limit the field of view (FOV), introduce return signal ambiguity, and reduce the optical efficiency in lidar applications. We demonstrate a Vernier transceiver scheme which uses paired transmit and receive phased arrays with different row periodicities, leading to mismatched grating lobe angular spacings and only a single aligned pair of transmit and receive lobes. This permits a return signal from a target in the desired lobe to be efficiently coupled back into the receive OPA while back-scatter from the other grating lobes is rejected, removing the ambiguity. Our proposal goes beyond previously considered Vernier schemes in other domains like RF and sound, to enable a dynamic Vernier where all beam directions are simultaneously Vernier aligned, and allow ultra-fast scanning, or multi-beam, operation with Vernier lobe suppression. We analyze two variants of grating lobe suppressing beam-steering configurations, one of which eliminates the FOV limitation, and find the conditions for optimal lobe suppression. We present the first, to the best of our knowledge, experimental demonstration of an OPA Vernier transceiver, including grating lobe suppression of 6.4 dB and beam steering across 5.5&deg;. The demonstration is based on a pair of 2D-wavelength-steered serpentine OPAs. These results address the pervasive issue of grating lobes in integrated photonic lidar schemes, opening the way to larger FOVs and reduced complexity 2D beam-steering designs. &nbsp;</p

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process&nbsp;technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics