Lattice study on a tetraquark state TbbT_{bb} in the HAL QCD method

The 39th International Symposium on Lattice Field Theory (LATTICE2022)We investigate a doubly-bottomed tetraquark state $T_{bb}$ $(bb bar{u}bar{d})$ with quantum number $I(J^P)=0(1^+)$ in $(2+1)$-flavor lattice QCD. Using the Non-Relativistic QCD (NRQCD) quark action for $b$ quarks, we have extracted the coupled channel potential between $bar{B}bar{B}^*$ and $bar{B}^* bar{B}^*$ in the HAL QCD method at $a approx 0.09$ {fm} on $32^3times 64$ lattices. The potential predicts an existence of a bound $T_{bb}$ below the $bar{B}bar{B}^*$ threshold. At the physical pion mass $m_piapprox140$ {MeV} extrapolated from $m_piapprox 410, , 570, , 700$ {MeV}, a binding energy with its statistical error is given by $E_{rm binding}^{rm (coupled)} = 83(10)$ MeV from a coupled channel analysis where effects due to virtual $bar{B}^* bar{B}^*$ states are included through the coupled channel potential, while we obtain $E_{rm binding}^{rm (single)} = 155(17)$ MeV only from a potential for a single $bar{B}bar{B}^*$ channel. This difference indicates that the effect from virtual $bar{B}^* bar{B}^*$ states is sizable to the binding energy of $T_{bb}$. Adding $pm 20$ MeV as empirical systematic error caused by the NRQCD approximation for $b$ quarks, our estimate of the $T_{bb}$ binding energy becomes $83(10)(20)$ MeV

Lattice study on a tetra-quark state TbbT_{bb} in the HAL QCD method

We study a doubly-bottomed tetra-quark state $(bb\bar{u}\bar{d})$ with quantum number $I(J^P)=0(1^+)$, denoted by $T_{bb}$, in lattice QCD with the Non-Relativistic QCD (NRQCD) quark action for $b$ quarks. Employing $(2+1)$-flavor gauge configurations at $a \approx 0.09$ {fm} on $32^3\times 64$ lattices, we have extracted the coupled channel potential between $\bar{B}\bar{B}^*$ and $\bar{B}^* \bar{B}^*$ in the HAL QCD method, which predicts an existence of a bound $T_{bb}$ below the $\bar{B}\bar{B}^*$ threshold. By extrapolating results at $m_\pi\approx 410,\, 570,\, 700$ {MeV} to the physical pion mass $m_\pi\approx140$ {MeV}, we obtain a biding energy with its statistical error as $E_{\rm binding}^{\rm (single)} = 155(17)$ MeV and $E_{\rm binding}^{\rm (coupled)} = 83(10)$ MeV, where ``coupled" means that effects due to virtual $\bar{B}^* \bar{B}^*$ states are included through the coupled channel potential, while only a potential for a single $\bar{B}\bar{B}^*$ channel is used in the analysis for ``single". A comparison shows that the effect from virtual $\bar{B}^* \bar{B}^*$ states is quite sizable to the binding energy of $T_{bb}$. We estimate systematic errors to be $\pm 20$ MeV at most, which are mainly caused by the NRQCD approximation for $b$ quarks.Comment: 27 pages, 8 figure

Practical Uses of A Semi-automatic Video Object Extraction System

Object-based technology is important for computer vision applications including gesture understanding, image recognition, augmented reality, etc. However, extracting the shape information of semantic objects from video sequences is a very difficult task, since this information is not explicitly provided within the video data. Therefore, an application for exttracting the semantic video object is indispensable and important for many advanced applications. An algorithm for semi-automatic video object extraction system has been developed. The performance measures of video object extraction system; including evaluation using ground truth and error metric is shown, followed by some practical uses of our video object extraction system. The principle at the basis of semi-automatic object extraction technique is the interaction of the user during some stages of the segmentation process, whereby the semantic information is provided directly by the user. After the user provides the initial segmentation of the semantic video objects, a tracking mechanism follows its temporal transformation in the subsequent frames, thus propagating the semantic information. Since the tracking tends to introduce boundary errors, the semantic information can be refreshed by the user at certain key frame locations in the video sequence. The tracking mechanism can also operate in forward or backward direction of the video sequence. The performance analysis of the results is described using single and multiple key frames; Mean Error and “Last_Error”, and also forward and backward extraction. To achieve best performance, results from forward and backward extraction can be merged

Anti-inflammatory Properties of Skeletal Muscle Protects Against Muscle Wasting in Colitis of Dextran Sulfate Sodium Model Mice

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A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths --- Toward Efficient CBC-Mode Implementation

This paper proposes a highly efficient AES hardware architecture that supports both encryption and decryption for the CBC mode. Some conventional AES architectures employ pipelining techniques to enhance the throughput and efficiency. However, such pipelined architectures are frequently unfit because many practical cryptographic applications work in the CBC mode, where block-wise parallelism is not available for encryption. In this paper, we present an efficient AES encryption/decryption hardware design suitable for such block-chaining modes. In particular, new operation-reordering and register-retiming techniques allow us to unify the inversion circuits for encryption and decryption (i.e., SubBytes and InvSubBytes) without any delay overhead. A new unification technique for linear mappings further reduces both the area and critical delay in total. Our design employs a common loop architecture and can therefore efficiently perform even in the CBC mode. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and the most efficient in terms of throughput per area among conventional AES encryption/decryption architectures with tower-field S-boxes. We evaluate the performance of the proposed and some conventional datapaths by logic synthesis results with the TSMC 65-nm standard-cell library and NanGate 45- and 15-nm open-cell libraries. As a result, we confirm that our proposed architecture achieves approximately 53--72% higher efficiency (i.e., a higher bps/GE) than any other conventional counterpart

A Fast Runtime Visualization of a GPU-Based 3D-FDTD Electromagnetic Simulation

In this paper, we present design and implementation of a fast runtime visualizer for a GPU-based 3D-FDTD electromagnetic simulation. We focus on improving the productivity of simulator development without compromising simulation performance. In order to keep the portability, we implemented a visualizer with the MVC model, where simulation kernels and visualization process were completely separated. For high-speed visualization, an interoperability mechanism between OpenGL and CUDA was used in addition to efficient utilization of programmable shaders. We also propose an asynchronous multi-threaded execution with a triple-buffering technique so that developers can concentrate on developing their simulation kernels. As a result of empirical visualization experiments of electromagnetic simulations for practical antenna design, it was revealed that our implementation achieved a rendering throughput of 90 FPS for a view port of 512 x 512 pixels, which corresponds to a 12.9 times speedup compared to when the OpenGL-CUDA interoperability mechanism was not utilized. When a standard visualization throughput of 60 FPS was selected, the performance overhead imposed by the visualization process was 15.8%, which was reasonably low compared to a speedup of the simulation kernel gained by the GPU acceleration

Highly Efficient GF(2^8) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design

This paper proposes a compact and efficient GF(2^8) inversion circuit design based on a combination of non-redundant and redundant Galois Field (GF) arithmetic. The proposed design utilizes redundant GF representations, called Polynomial Ring Representation (PRR) and Redundantly Represented Basis (RRB), to implement GF(2^8) inversion using a tower field GF((2^4)^2). In addition to the redundant representations, we introduce a specific normal basis that makes it possible to map the former components for the 16th and 17th powers of input onto logic gates in an efficient manner. The latter components for GF(2^4) inversion and GF(2^4) multiplication are then implemented by PRR and RRB, respectively. The flexibility of the redundant representations provides efficient mappings from/to the GF(2^8). This paper also evaluates the efficacy of the proposed circuit by means of gate counts and logic synthesis with a 65 nm CMOS standard cell library and comparisons with conventional circuits, including those with tower fields GF(((2^2)^2)^2). Consequently, we show that the proposed circuit achieves approximately 40% higher efficiency in terms of area-time product than the conventional best GF(((2^2)^2)^2) circuit excluding isomorphic mappings. We also demonstrate that the proposed circuit achieves the best efficiency (i.e., area-time product) for an AES encryption S-Box circuit including isomorphic mappings