The Department of Electrical and Computer Engineering Newsletter

Summer 2017 News and notes for University of Dayton\u27s Department of Electrical and Computer Engineering.https://ecommons.udayton.edu/ece_newsletter/1010/thumbnail.jp

The Circuit, Spring 2017

Table of Contents: Early Career Awards Spotlighting: Leonard Bohman Visiting Faculty Bridging Past and Future Through Automation Robotics Systems Enterprise Inspiring the Next Generation Tech Team Wins Team Tech Ramping Up Automotive Controls Bucheger Moves Senior Design Forward Student News Alumni Newshttps://digitalcommons.mtu.edu/ece-newsletters/1004/thumbnail.jp

Electrical and Computer Engineering Annual Report 2018

Welcome New President and Dean Faculty Directory Faculty Highlights Exciting Challenges for Expert Teacher Mobility Research: Sumit Paudyal Mobility Research: Chee-Wooi Ten Mobility Research: Bruce Mork Faculty Profile and Department Award Faculty Publications Staff Profile and Directory Graduate Student Awards and Degrees Student Highlights Senior Design Enterprise Enterprise and Undergraduate Student Awards ECE Academy Class of 2018 External Advisory Committee Contracts and Grants Department Statisticshttps://digitalcommons.mtu.edu/ece-annualreports/1000/thumbnail.jp

Electrical and Computer Engineering Annual Report 2015

Faculty Directory Faculty Awards Google ATAP—Michigan Tech MURA The Sound Beneath the Surface Advancing Microgrid Deployment Clearing the Air Power in Their Hands Faculty Publications Graduate Student Highlights Staff Profile—Chito Kendrick New ECE Concentrations SLAM Systems Senior Design and Enterprise External Advisory Committee Contracts and Grants Departmental Statistics Lind Memorial Endowed Fellowshiphttps://digitalcommons.mtu.edu/ece-annualreports/1003/thumbnail.jp

The Department of Electrical and Computer Engineering Newsletter

Fall 2011 News and notes for University of Dayton\u27s Department of Electrical and Computer Engineering.https://ecommons.udayton.edu/ece_newsletter/1000/thumbnail.jp

The Department of Electrical and Computer Engineering Newsletter

Spring 2017 News and notes for University of Dayton\u27s Department of Electrical and Computer Engineering.https://ecommons.udayton.edu/ece_newsletter/1011/thumbnail.jp

Layer assignment and routing optimization for advanced technologies

As VLSI technology scales to deep sub-micron and beyond, it becomes increasingly challenging to achieve timing closure for VLSI design. Since a complete design flow consists of several phases, such as logic synthesis, placement, and routing, interconnect synthesis plays an important role which includes buffer insertion/sizing and timing-driven routing. Although progress has been achieved by many advanced routing techniques, the following aspects can be exploited sufficiently for further improvement: (1) incremental layer assignment for timing optimization; (2) signal routing with the requirement of regularity; (3) power-efficient optical-electrical interconnect paradigm. Thus, to perform the layer assignment and routing optimization for advanced technologies, an automated routing engine in a global view is essential to benefit the interconnect design while satisfying specific requirements. This dissertation proposes a set of algorithms and methodology on layer assignment and routing optimization for advanced technologies. The research includes two timing-driven incremental layer assignment approaches, synergistic topology generation and routing synthesis for signal groups, and optical-electrical routing design for power efficiency. For incremental layer assignment, most of the conventional approaches target via minimization but neglect the timing issues. Meanwhile, via delays are ignored but should be considered in emerging technology nodes. Then two timing-driven incremental layer assignment frameworks are proposed, where all the nets are solved simultaneously with the integration of via delays: (1) optimization of the total sum of net delays and reduction of slew violations; (2) minimization of critical path timing in selected nets. For on-chip signal routing, the bundled bits in one group may have different pin locations, but they have to be routed in a regular manner by sharing common topologies. Very few previous works target inter-bit regularity via multi-layer topology selection. Furthermore, the routability and wire-length of the signal bits should also be optimized. Then an advanced synergistic routing engine is promoted, which is able to not only control routability and wire-length but also guide each bit routing intelligently for design regularity. For optical-electrical co-design routing, optical interconnect shows its advantage due to the dominance of bandwidth-distance-power properties. The previous works lack a detailed exploration of optical-electrical co-design for on-chip interconnects. During the transmission, signal quality can be affected by various loss sources and Electrical to Optical (EO)/Optical to Electrical (OE) conversion overheads should also be considered. Then a power-efficient routing flow for on-chip signals is presented, where optical connections can collaborate with electrical wires seamlessly. The effectiveness of proposed algorithms and techniques is demonstrated in this dissertation. These approaches are able to achieve the improvements regarding specific metrics and eventually benefit the routing flow.Electrical and Computer Engineerin