Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures

Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability. Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well. Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic

Characterization of Nanomaterials: Selected Papers from 6th Dresden Nanoanalysis Symposiumc

This Special Issue “Characterization of Nanomaterials” collects nine selected papers presented at the 6th Dresden Nanoanalysis Symposium, held at Fraunhofer Institute for Ceramic Technologies and Systems in Dresden, Germany, on 31 August 2018. Following the specific motto of this annual symposium “Materials challenges—Micro- and nanoscale characterization”, it covered various topics of nanoscale materials characterization along the whole value and innovation chain, from fundamental research up to industrial applications. The scope of this Special Issue is to provide an overview of the current status, recent developments and research activities in the field of nanoscale materials characterization, with a particular emphasis on future scenarios. Primarily, analytical techniques for the characterization of thin films and nanostructures are discussed, including modeling and simulation. We anticipate that this Special Issue will be accessible to a wide audience, as it explores not only methodical aspects of nanoscale materials characterization, but also materials synthesis, fabrication of devices and applications

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Mechanical analysis of a heterogeneously integrated silicon photonic interposer

Overcoming the bandwidth bottleneck in conventional interconnects necessitates transitioning to alternative scaling paradigms. Silicon (Si) photonics is considered a disruptive technology, capable of meeting the growing demands for higher bandwidth, low latency, and power efficiency. By leveraging the intrinsic properties of optical signals and manufacturing compatibility of Si, the co-integration of Si photonics and complementary-metal-oxide-semiconductor (CMOS) circuitry leading to terabit data speeds for next generation data communication can be realized. Heterogeneously integrating Si photonic functionality with well-established CMOS technology in an Si photonic interposer architecture simultaneously provides independent optimization as well as close integration of both technologies in one platform. The Si photonic interposer architecture is comprised of a photonic wafer that is SiO2- SiO2 bonded to a through silicon via (TSV) interposer. Electrical interfacing between attached die, active photonic devices, and the TSV interposer are established with the use of compact 2 μm diameter through-oxide-vias (TOV). The TOV has ultra-low capacitance (1.45 pf) and minimal parasitic capacitance (~3pf) which is critical for next generation highly compact optical systems. Stress generation from TOV annealing can effect light propagation in optical devices due to the photo-elastic effect. This can manifest as weak mode confinement, wavelength shifts, multimode propagation, and several optical loss mechanisms

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future

Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems

Three-Dimensional NoC Reliability Evaluation Automated Tool (TREAT)

Technology scaling and higher operational frequencies are no longer sustainable at the same pace as before. The processor industry is rapidly moving from a single core with high-frequency designs to many-core with lower frequency chips; Network-on-Chip (NoC) has been proposed as a scalable and efficient on-chip interconnection among cores. In addition, employing Three-Dimensional (3D) integration instead of Two-Dimensional (2D) integration is the other trend to keep the traditional expected performance improvements. The combination of 3D integration and NoC technologies provides a new horizon for on-chip interconnect design. In more detail, the reduction of the length and number of global interconnects; by applying Through-Silicon Via (TSV) is the major advantage of 3D NoCs.However, shrinking transistor sizes, smaller interconnect features, and 3D packaging issues, lead to higher error rates and unexpected timing variations. Although many researches have focused on reliability issues for 3D NoC architectures, To develop a general technique to advance both the intuitive understanding and the quantitative measurement of how potential physical faults influence the behavior of 3D NoC is lacking. The goal of my dissertation is to develop a Three-Dimensional NoC Reliability ity Evaluation Automated Tool (TREAT), for the first time, as an automated analysis tool to analyze effects of static and dynamic faults in 3D NoC architectures. It is capable of evaluating the vulnerability of different architectural components in the presence of faults by using the fault injection method. This approach allows injecting faults into the 3D NoC platform dynamically by monitoring the status of links and components to decide where and when inject faults accurately. TREAT provides the strength of different components in terms of reliability-based metrics such as Mean Time Between Failure (MTBF) and header/data/trailer flit failure rate for different level of granularity. The output reports of TREAT are critical in devising fault-tolerant techniques with low overhead cost. TREAT can be used at the early stage of the design process in order to prevent costly redesigns after assessing dependability for the target architecture.Comparing to existing fault injector tools, TREAT is specifically developed for 3D NoC platforms and it is not a general fault injector tool. Such a tool is needed since the characteristics and behavior of a 3D NoC component is different from other computational platforms; 3D NoCs are susceptible to different fault sources that are notfully addressed by existing tools. Furthermore, one of the most important advantages of TREAT is supporting dynamic fault injection by monitoring the status of the NoC platform. This is critical since based on the reported experiments in this dissertation, random TSV coupling fault injection may result in 26%-99% inaccuracy of reliability evaluation process. The fault injector interface is responsible for injecting fault accurately where and when they should in order to enhance the reliability evaluation. None of the existing tools offer these capabilities as a single package