REDUCING TRANSISTOR COUNT IN CMOS LOGIC DESIGN THROUGH CLUSTERING, SUPERCLUSTERING, AND SOP SPLITTING

Abstract

Transistor-level synthesis is crucial for designing digital circuits because it allows for precise control over the behavior and performance of the circuit at the most fundamental level. This detailed design approach enables optimization of power consumption, speed, and area, leading to highly efficient and compact circuits. By directly manipulating the transistors, designers can achieve tailored solutions that meet specific performance requirements and constraints, which is essential for advanced applications such as high-speed processors, low-power devices, and complex integrated systems. Moreover, transistor-level synthesis helps identify and mitigate potential issues like signal integrity problems and parasitic effects early in the design process, ensuring robust and reliable circuit operation. The first contribution of this dissertation, presented in Chapter 2, is the proposal of a novel transistor-level synthesis method designed to minimize the number of transistors needed to implement a digital circuit. In contrast with traditional standard cell design methods or transistor-level synthesis methods based on “complex” gates or “super” gates, our method considers multioutput clusters as the basic resynthesis unit. Our tool takes any gate-level circuit netlist as input and divides it into several clusters of user-controlled size. For each output of a cluster, a simplified sum of product (SOP) expression is obtained, and all such expressions are jointly minimized for the cluster using the MOTO-X multi-output transistor-level synthesis tool. Since the polarity of the cluster outputs affects the number of transistors required for the multi-output transistor network, we obtain a minimized transistor count for each output polarity combination (“opc”) of the cluster outputs. By choosing the lowest transistor count implementation of each cluster, we identify a suitable transistor cost implementation for the complete circuit. Experimental results indicate average transistor count reductions compared to the ABC synthesis tool of 7.39%, 0.27%, 6.15%, and 4.24% for the ISCAS’85, LGSynth’89, LGSynth’91 and ITC’99 benchmark suites, respectively. The second contribution of this dissertation, presented in Chapter 3, introduces the concept of ‘superclusters.’ This approach moves beyond optimizing the opc implementation of individual clusters, by considering groups of related clusters. By minimizing input-output inversion costs and selecting optimal output polarity combinations for each cluster within the supercluster, the method achieves a significantly reduced overall transistor count for the circuit implementation. Experimental results demonstrate average transistor count reductions of 9.95%, 6.57%, 10.50%, 9.76%, and 13.09% compared to the ABC synthesis tool for the ISCAS’85, LGSynth’89, LGSynth’91, ITC’99, and EPFL’15 benchmark suites, respectively. The final contribution of this dissertation, presented in Chapter 4, proposes a novel transistor-level synthesis method based on SOP splitting to minimize the number of transistors required for digital circuit implementation. Unlike traditional boolean function factoring heuristics, our approach treats multi-output clusters as the fundamental units for resynthesis, then splits the SOP function of the output with user-defined constraints. These expressions are then collectively minimized for each cluster using the MOTO-X multi-output transistor-level synthesis tool. Additionally, we use superclustering technique of Chapter 3 to optimize groups of related clusters together to reduce transistor count further. Experimental results show that our method achieves average transistor count reductions of 8.59%, 1.93%, 6.22%, and 7.76% compared to the ABC synthesis tool for the ISCAS’85, LGSynth’89, LGSynth’91, and ITC’99 benchmark suites, respectively. Additionally in Chapter 5, we demonstrate the power and delay analysis results of circuit clusters obtained by our proposed method versus ABC synthesis tool’s optimized circuits. Highlighting the potential of our methodology for optimizing integrated circuits at the transistor-level while concurrently delivering enhancements in both power efficiency and delay