Thermal Control and Optimization for Assembled Photonic Interconnect Systems


In recent years, there has been significant progress in the development of integrated photonic circuits (PICs). Matured fabrication and simulation techniques have enabled the development of novel devices and system architectures. Ideally, these newly developed technologies are put to test in the lab, both to verify that they perform as simulated and to demonstrate the viability of the technology. Testing the increasingly complex optical circuits brings various challenges. One of these challenges is the sensitivity to temperature changes of many optical circuits, especially micro ring and micro disk resonators (MRRs and MDRs). Due to the nature of these resonators, slight deviations in the material properties have a large impact on their resonant frequency. Despite this, their small footprint and wavelength selectivity makes them promising components for many future technologies, especially Dense Wavelength Division Multiplexed (DWDM) communication links. Multiple resonators cascaded on a single bus waveguide can operate on multiple wavelengths simultaneously with relatively few components and in a small combined area. Since every extra connection to a PIC has a footprint similar to that of a micro resonator, a packaging optimized thermal control scheme is needed to fully leverage all advantages of micro resonators. This work will focus on the thermal stabilization of cascaded micro resonators and how thermal control can be optimized to simplify the packaging of PIC prototypes. This simplification enables the demonstration of complex systems and more realistic scenarios for thermal control of both resonators and other circuits. It will first show how a number of PICs and their respective packages were built, keeping subsequent testing in mind. Then, it demonstrates automatic initialization of cascaded MRR and how stable operation, while undergoing large temperature swings, can be achieved using a minimum number of connections to the PIC. Next, it shows stable operation of an eight-wavelength receiver, operating uncooled at 16 Gb/s/?, over a record 75 °C. Finally, it presents how all the learned lessons are brought together to built a 2.5D integrated SiPh transceiver that is capable of transmitting 512 Gb/s bidirectionally. This transceiver can be plugged into Field Programmable Gate Arrays (FPGAs), which can then be used to implement accelerators for real computing problems, used as a PCIe bridge to a standard compute server, or both. The transceiver is also designed to work with many types of optical switches, allowing demonstrations of novel switching algorithms and network architectures. The contributions discussed in this thesis can assist in enabling future high bandwidth optical interfaces by optimizing the thermal control strategy and may be used at all stages of PIC design and packaging to facilitate the development of new technologies

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Columbia University Academic Commons


This paper was published in Columbia University Academic Commons.

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